• 제목/요약/키워드: redundant architecture

검색결과 93건 처리시간 0.022초

고속 네트워크 시스템의 이중화 회로 구현 (Implementation of High Speed Router's Redundancy Architecture)

  • 강덕기;이상우;이준철;이형섭;이영천
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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    • pp.267-270
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    • 2000
  • In this paper, we consider the simple redundant structures with the function of hardware based active/standby control. The system includes two switch modules. The switch module is connected to a data bus, but only the active switch module has control of the data bus. The standby unit takes over the function of the active unit when the active unit failure or mode command are asserted. And this paper illustrate the high-speed router system and the overall redundant system architecture. The proposed redundant architecture for 80G Router system is verified and implemented with experiment.

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경기도 토지이용규제 현황과 문제점 고찰 (A Case Study on the Status and Problems of Regulations of Land Use in Gyeonggi-do)

  • 김영훈;권경남
    • KIEAE Journal
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    • 제16권6호
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    • pp.57-67
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    • 2016
  • Purpose: Laws and regulations of land use are enormous, and the appliance of regulations is overlapped redundantly. Therefore, there are many problems such as time consuming in the process, limiting individual property rights, and interrupting enterprises' economic activities. This study will discuss problems of redundant regulations of land use and its improvement by figuring out current regulations of land use in Gyeonggi-do, one of provinces which applies the most various regulations of land use. Method: This study reviews laws on national land-use planning system and characteristics of land-use regulation in Korea. The extent of the review is limited to "framework act on the regulation of land use" with categories of national land, urban planing, architecture, etc. Through case studies in Gyeonggi-do, the status and problems of redundant regulations of land use are defined. For example, it is overlapped in "Seoul Metropolitan Area Readjustment Planning Act", Development Restriction Zone, Paldang Special District, and so on. It is mainly referred to 2015 Gyeonggi-do land-use restriction map. Result: First, Gyeonggi-do confronts many problems related to the development restrictions and the financial increasement for environmental management by redundant regulations. The development restrictions include supplying additional land for industrial use, relocating colleges, and height limitation relating to military facilities. Second, in order to organize redundant regulations, it is required to combine similar regulations and adjust through communication system among other departments. Third, regulations should consider unique local condition of each district. Lastly, efficient application of regulations is necessary so as to maximize the function of land, protect individual property rights, and stimulate local development.

Redundant Signed Binary Number에 의한 CORDIC 회로 (The CORDIC Circuit of Redundant Signed Binary Number)

  • 김승열;김용대;한선경;유영갑
    • 전자공학회논문지CI
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    • 제40권6호
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    • pp.1-8
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    • 2003
  • Global carry propagation이 없는 redundant signed number에 의한 CORDIC 회로를 제안하였다. 이 number format은 Booth recording과 유사한 새로운 receding scheme을 가지고 가감산에서 carry 전파의 문제를 효과적으로 해결하였다. 여기서는 상수 scale factor를 갖고 삼각함수 계산을 하는 pipeline구조를 채택하였다. 이 CORDIC 회로의 동작시간은 채택한 operand bit에 상관없이 일정하다.

항공전자 시스템을 위한 PCI-Express 버스의 결함감내 구조 (A Fault-Tolerant Architecture of PCI-Express Bus for Avionics Systems)

  • 김성준;김경훈;전용기
    • 한국항공우주학회지
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    • 제48권12호
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    • pp.1005-1012
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    • 2020
  • PCI-Express 버스를 적용하는 항공전자 시스템은 CPU와 입출력 장치를 하나의 채널만을 사용하여 연결하기 때문에, 불행하게도 그 채널에 고장이 발생하면 적어도 하나의 입출력 장치를 사용할 수 없게 되는 문제가 있다. 본 논문은 항공전자 시스템을 위한 PCI-Express 버스의 결함감내 구조를 제시하기 위해서, PCI-Express 채널을 이중화하여 하나의 채널에 고장이 발생하여도 고장이 발생하지 않은 다른 채널을 통해 여전히 정상적으로 기능하는 버스 구조를 제시한다. 논문에서 제시하는 버스 구조는 두 개의 CPU port에서 출력된 이중적 PCI-Express 버스 신호를 각각의 switch 회로에 입력되게 하고, 이 회로가 각 입출력 장치에 결함을 감내하도록 선택된 독립된 버스 채널을 제공하게 한다. 본 논문에서는 제시하는 버스 구조를 구현 및 실험하여 하나의 PCI-Express 버스에 고장이 발생하면, 그 고장 상황을 실시간으로 감지되고, 고장이 발생하지 않은 다른 버스로 채널을 전환되어 정상적으로 통신이 수행되는 것을 보인다.

Performance validation and application of a mixed force-displacement loading strategy for bi-directional hybrid simulation

  • Wang, Zhen;Tan, Qiyang;Shi, Pengfei;Yang, Ge;Zhu, Siyu;Xu, Guoshan;Wu, Bin;Sun, Jianyun
    • Smart Structures and Systems
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    • 제26권3호
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    • pp.373-390
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    • 2020
  • Hybrid simulation (HS) is a versatile tool for structural performance evaluation under dynamic loads. Although real structural responses are often multiple-directional owing to an eccentric mass/stiffness of the structure and/or excitations not along structural major axes, few HS in this field takes into account structural responses in multiple directions. Multi-directional loading is more challenging than uni-directional loading as there is a nonlinear transformation between actuator and specimen coordinate systems, increasing the difficulty of suppressing loading error. Moreover, redundant actuators may exist in multi-directional hybrid simulations of large-scale structures, which requires the loading strategy to contain ineffective loading of multiple actuators. To address these issues, lately a new strategy was conceived for accurate reproduction of desired displacements in bi-directional hybrid simulations (BHS), which is characterized in two features, i.e., iterative displacement command updating based on the Jacobian matrix considering nonlinear geometric relationships, and force-based control for compensating ineffective forces of redundant actuators. This paper performs performance validation and application of this new mixed loading strategy. In particular, virtual BHS considering linear and nonlinear specimen models, and the diversity of actuator properties were carried out. A validation test was implemented with a steel frame specimen. A real application of this strategy to BHS on a full-scale 2-story frame specimen was performed. Studies showed that this strategy exhibited excellent tracking performance for the measured displacements of the control point and remarkable compensation for ineffective forces of the redundant actuator. This strategy was demonstrated to be capable of accurately and effectively reproducing the desired displacements in large-scale BHS.

Analysis of the redundant architecture for the fault-tolerance of a distributed control system

  • Moon, Hong-ju
    • 한국신뢰성학회:학술대회논문집
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    • 한국신뢰성학회 2000년도 춘계학술대회 발표논문집
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    • pp.231-238
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    • 2000
  • The distributed digital control system has many shared common components, and a single fault in the system may have effects on not a single function. Not as in an analog system, the faults in a digital system usually make discrete and abrupt changes in its output, which are hard to be expected. To cope with these situations, the fault-tolerance is an inevitable property of a distributed control system. A distributed digital control system consists of many equipments, and each equipment can be implemented by many different technologies. The fault-tolerance has to be implemented depend-ing on the overall architecture and how each equipment is implemented. The paper analyzes and compares the strategies and tactics to add the fault-tolerances in a distributed digital control system, and studies how they can be combined appropriately.

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Redundant phase center 기법과 phase gradient autofocus를 이용한 합성개구소나 영상 보정 (A correction of synthetic aperture sonar image using the redundant phase center technique and phase gradient autofocus)

  • 유정수;백경민
    • 한국음향학회지
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    • 제40권6호
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    • pp.546-554
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    • 2021
  • 수중 탐지를 위한 합성개구소나(Synthetic Aperture Sonar, SAS) 신호처리에서는 탑재플랫폼이 직선경로를 따라 주행한다고 가정한다. 그러나 실제로는 플랫폼의 복잡한 운동에 따른 궤적 교란으로 인해 SAS 영상에 번짐과 같은 왜곡이 발생한다. 본 연구에서는 예인형 SAS 개발을 위해 궤적 교란에 의한 SAS 영상 왜곡을 개선하기 위한 방법으로서, Redundant Phase Center (RPC)을 이용한 예인체 운동 추정 및 영상 보정, 그리고 자동 초점 기법인 Phase Gradient Autofocus (PGA) 기법에 대해 검토하였다. 그리고 시뮬레이션을 통해, sway로 인해 왜곡된 SAS 영상에 이 기법들을 적용하고 그 성능 및 유효성에 대해 살펴보았다.

Redundant binary 연산을 이용한 고속 복소수 승산기 (A high-speed complex multiplier based on redundant binary arithmetic)

  • 신경욱
    • 전자공학회논문지C
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    • 제34C권2호
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    • pp.29-37
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    • 1997
  • A new algorithm and parallel architecture for high-speed complex number multiplication is presented, and a prototype chip based on the proposed approach is designed. By employing redundant binary (RB) arithmetic, an N-bit complex number multiplication is simplified to two RB multiplications (i.e., an addition of N RB partial products), which are responsible for real and imaginary parts, respectively. Also, and efficient RB encoding scheme proposed in this paper enables to generate RB partial products without additional hardware and delay overheads compared with binary partial product generation. The proposed approach leads to a highly parallel architecture with regularity and modularity. As a results, it results in much simpler realization and higher performance than the classical method based on real multipliers and adders. As a test vehicle, a prototype 8-b complex number multiplier core has been fabricated using $0.8\mu\textrm{m}$ CMOS technology. It contains 11,500 transistors on the area of about $1.05 \times 1.34 textrm{mm}^2$. The functional and speed test results show that it can safely operate with 200 MHz clock at $V_{DD}=2.5 V$, and consumes about 90mW.

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Dual Mode Control for the Robot with Redundant Degree of Freedom -The application of the preview learning control to the gross motion part-

  • Mori, Yasuchika;Nyudo, Shin
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 19-21 Oct. 1992
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    • pp.296-300
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    • 1992
  • This paper deals with a dual mode control system design for the starching work robot. From the feature of this work, the robot has redundant degree of freedom. In this paper, we try to split the whole movement the robot into a gross motion part ai. a fine motion part so as to achieve a good tracking performance. The preview learning control is applied to the gross motion part. The validity of the dual mode control architecture is demonstrated.

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불필요한 연산이 없는 카라슈바 알고리즘과 하드웨어 구조 (An Efficient Architecture for Modified Karatsuba-Ofman Algorithm)

  • 장남수;김창한
    • 대한전자공학회논문지SD
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    • 제43권3호
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    • pp.33-39
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    • 2006
  • Divide-and-Conquer방법은 병렬 곱셈기의 구성에 잘 적용되며 가장 대표적으로 카라슈바 방법이 있다. Leone은 최적 반복 회수를 카라슈바 알고리즘에 적용하였으며 Ernst는 다중 분할 카라슈바 방법을 제안하였다. 본 논문에서는 카라슈바 알고리즘에서 불필요한 연산이 제거된 불필요한 연산이 없는 카라슈바 알고리즘과 효율적인 하드웨어 구조를 제안한다. 본 논문에서 제안하는 알고리즘은 기존의 카라슈바 알고리즘에 비교하여 같은 시간 복잡도를 가지나 공간 복잡도를 효율적으로 감소시킨다. 특히 확장체의 차수 n이 홀수 및 소수일 때 더 효율적이며 최대 43%까지 공간 복잡도를 줄일 수 있다.