• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.96-103
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• 2006

This paper proposes a new technique for improving the efficiency of single phase high frequency switch mode boost converter. This converter includes an additional boost converter that follows the main hish frequency switching device. The additional converter, which is controlled at lower frequencies, bypasses almost all the current in the main switch and the high frequency switching loss is greatly reduced. Both switching devices are controlled by a simple method; each controller consists of a one-shot multivibrator, a comparator and an AND gate, and the maximum switching frequency can be limited without any clock generator. The converter works cooperatively in high efficiency and acts as though it were a conventional high frequency switch mode converter with one switching device. This paper describes the proposed converter configuration, design, and discusses the steady state performance concerning the switching loss reduction and efficiency improvement. and the proposed method is verified by computer simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.6
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• pp.474-480
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• 2001

In this paper a low signal reduction communication system that does not use the communication line but power line is presented It will be very useful for an information-oriented society with tele-metering and home automation. The conventional system has a difficulty in transmitting information due to decreasing communication voltage. The proposed system employs a special type switching amplifier system which has a low inner resistance and uses high efficient ferrite core in coupling circuit. This new system is proposed to reduce the loss of conductor load and coupling circuit in a PLC system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.50-57
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• 2008

In this paper, a high-efficiency charge pump for use in CMOS image sensor(CIS) is proposed. The proposed charge pump pursues high pumping efficiency by minimizing the switching and reversion losses by taking advantage of operation characteristics of CIS. That is, the proposed charge pump minimizes the switching loss by dynamically controlling the size of clock driver, pumping capacitor, and charge transfer switch based on the operation phase of CIS pixel sensor. The charge pump also minimizes the reversion loss by guaranteeing a sufficient non-overlapping period of local clocks using a tri-state local clock driver adapting the schmitt trigger. Comparison results using a 0.13-um CMOS process technology indicate that the proposed charge pump achieves up to 49.1% reduction on power consumption under no loading current condition as compared to conventional charge pump. They also indicate that the charge pump provides 19.0% reduction on power consumption under the maximum loading current condition.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1963-1965
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• 1998

In this paper, a new simplified configuration for a multi-level PWM inverter is proposed. The proposed inverter consists of an auxiliary circuit with one switching device, and 3 phase full-bridge inverter. The proposed inverter, in spite of reduction of the switching devices, offers characteristics similar to the NPC(Neutral - point - clamped)- PWM inverter. Also, since the reduction of the switching devices, the control strategy is simplified. And switching loss is reduced. In addition to, it is possible that reliable DC level voltage than former multi-level inverter. And load power application is same to conventional NPC-PWM inverter. The performance of the system is verified by simulation. In this paper, show the simulation result of the single phase full bridge inverter application.

• Proceedings of KOSOMES biannual meeting
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• 2017.04a
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• pp.220-220
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• 2017

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.4
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• pp.16-21
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• 2013

This paper presents a DC link voltage control method to reduce the ripple current and the switching loss in the sinusoidal current drive system for the wide-speed range PMSM. The DC link voltage of the three phase inverter in the sinusoidal current drive system is designed by the back-EMF voltage at maximum speed of the PMSM. In general, the drive systems have used the constant DC link voltage without reference to the motor speed. The current ripple causes hysteresis loss and makes noise. In addition, the switching loss on the inverter increases in proportion to the rise in the DC link voltage. In this paper, we propose the variable DC link voltage control method to reduce the current ripple in the PMSM drive system. We show reduction effect of the current repple and the switching loss through simulation results.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.279-281
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• 2001

This paper presents a chaotic neural networks to solve the distribution feeder reconfiguration problem for loss reduction. Feeder reconfiguration problem is the determination of switching option that minimizes the power losses for a particular set of loads in distribution systems. A chaotic neural networks is used to determine the switching combinations, select the status of the switches, and find the best combination of switches for minimum loss. The proposed method has been tested on 32 bus system, and the results indicate that it is able to determine the appropriate switching options for optimal configuration.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1640-1648
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• 2014

This paper proposes a switching frequency reduction method for MMC (Modular Multilevel Converter) utilizing redundancy operation of sub-module, which can offer reduction of voltage harmonics and switching loss. The feasibility of proposed method was verified through computer simulations with PSCAD/EMTDC software. Based on simulation analysis, a hardware scaled-model of 10kVA, DC-1000V MMC was designed and manufactured in the lab. Various experiments were conducted to verify the feasibility of proposed method in the actual hardware system. The hardware scaled-model can be effectively utilized for analyzing the performance of MMC according to the modulation scheme and redundancy operation.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1094-1096
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• 2002

A new technique for improving the efficiency of single-phase high-frequency boost converter is proposed. This converter includes an additional low-frequency boost converter which is connected to the main high-frequency switching device in parallel. The additional converter is controlled at lower frequency. Most of the current flows in the low-frequency switch and so, high-frequency switching loss is greatly reduced accordingly. Both switching device are controlled by a simple method; each controller consists of a comparator, a frequency generator and an error amplifier. The converter works cooperatively in high efficiency and acts as if it were a conventional high-frequency boost converter with one switching device, The proposed method is verified by simulation and experiment. This paper describes the converter configuration and design, and discusses the steady-state performance concerning the switching loss reduction and efficiency improvement.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.362-365
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• 1999

In this paper, the method of reducing harmonics and correcting of power factor in single PWM converter associated with diode rectifier and boos converter is studied. The ac-dc converter in which the harmonic distortion in the input current is reduced using a third harmonic injected PWM is proposed. A lower switching power loss and easy configuration o control circuit are obtained by adopting discontinuous current mode. Simulation and experimental results of ac-dc converter with 5[KHz] switching frequency are presented and correction of power factor and reduction of total harmonic distortion was established.