• International Journal of Control, Automation, and Systems
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• 제6권3호
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• pp.327-338
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• 2008

A fault tolerant control system design technique has been proposed and analyzed for managing performance degradation in the presence of multiple faults in actuators. The method is based on a control structure with a model reference reconfigurable control design in an inner loop and command input adjustment in an outer loop. The reduced dynamic performance requirements in the presence of different actuator faults are accounted for through different performance reduced (degraded) reference models. The degraded steady-state performances are governed by the reduced levels of command input. The reconfigurable controller is designed on-line automatically in an explicit model reference control framework so that the dynamics of the closed-loop system follow that of the performance reduced reference model under each fault condition. The reduced command input level is determined to prevent potential actuator saturation. The proposed method has been evaluated and analyzed using an aircraft example against actuator faults subject to constraints on the magnitude and slew-rate of actuators.

• 한국항공우주학회지
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• 제34권3호
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• pp.67-73
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• 2006

본 논문에서는 매개변수 추종기법과 모델추종 적응제어기법을 이용하여 재형상 모델 추종 비행제어기법을 제안하였다. 기준 모델을 추종하기 위하여 모델의 신호와 입력, 오차를 이용하여 적응제어기를 구성하였다. 고장이 발생하는 경우 시스템에 발생하는 불확실성에 대처하기 위해 시스템 식별기법을 도입하였으며, 역변환 계산의 용이성을 위해 회귀적 재귀 푸리에 변환기법을 사용하였다. 회귀적 재귀 푸리에 변환을 이용한 적응제어기법을 통해 고장에 능동적으로 대처하는 비행제어시스템을 구성하였으며, 항공기 제어면 파손을 모사하기 위하여 안정미계수 및 조종미계수 기법을 이용하여 고장을 정식화 하였다. 수치 시뮬레이션을 통해 제안된 제어시스템의 타당성을 검증하였다.

• Journal of Electrical Engineering and Technology
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• 제13권4호
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• pp.1740-1751
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• 2018

This paper proposes a novel fault tolerant tracking control (FTTC) scheme for a class of nonlinear systems with actuator failures based on the policy iteration (PI) algorithm and the adaptive fault observer. The estimated actuator failure from an adaptive fault observer is utilized to construct an improved performance index function that reflects the failure, regulation and control simultaneously. With the help of the proper performance index function, the FTTC problem can be transformed into an optimal control problem. The fault tolerant tracking controller is composed of the desired controller and the approximated optimal feedback one. The desired controller is developed to maintain the desired tracking performance at the steady-state, and the approximated optimal feedback controller is designed to stabilize the tracking error dynamics in an optimal manner. By establishing a critic neural network, the PI algorithm is utilized to solve the Hamilton-Jacobi-Bellman equation, and then the approximated optimal feedback controller can be derived. Based on Lyapunov technique, the uniform ultimate boundedness of the closed-loop system is proven. The proposed FTTC scheme is applied to reconfigurable manipulators with two degree of freedoms in order to test the effectiveness via numerical simulation.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.757-758
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• 2013

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.174-181
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• 2004

In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at $2{\sim}6$ GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation, $2{\sim}6$ GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.

• 대한산업공학회지
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• 제32권2호
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• pp.82-90
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• 2006

Reconfigurability of machine tools is one of the critical factors to realize the responsive manufacturing systems to satisfy the mass customization production. This paper presents the methods to model the reconfigurable machine tools (RMTs) on Internet in response to change in the machining requirements. Specifically, the structure and motion model of machine tools using module combination rules and connectivity graph are developed. And we developed Internet-based simulator for designing of RMTs (ISD-RMT). In response to the user requirements, various structures of RMTs can be derived using the module combination rules and connectivity graph relationships. In addition, the user can verify generating structures through the control and simulation procedures.

• ETRI Journal
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• 제38권4호
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• pp.654-664
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• 2016

This paper presents a transformer-based reconfigurable synchronous boost converter. The lowest maximum power point tracking (MPPT)-input voltage and peak efficiency of the proposed boost converter, 20 mV and 88%, respectively, were achieved using a reconfigurable synchronous structure, static power loss minimization design, and efficiency boost mode change (EBMC) method. The proposed reconfigurable synchronous structure for high efficiency enables both a transformer-based self-startup mode (TSM) and an inductor-based MPPT mode (IMM) with a power PMOS switch instead of a diode. In addition, a static power loss minimization design, which was developed to reduce the leakage current of the native switch and quiescent current of the control blocks, enables a low input operation voltage. Furthermore, the proposed EBMC method is able to change the TSM into IMM with no additional time or energy loss. A prototype chip was implemented using a $0.18-{\mu}m$ CMOS process, and operates within an input voltage range of 9 mV to 1 V, and an output voltage range of 1 V to 3.3 V, and provides a maximum output power of 37 mW.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.451-454
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• 2004

The reconfigurable architecture is increasingly important for design of multi-mode communication systems and computation-intensive DSP systems. The proposed coarse-grain architecture is based on a reconfigurable processing element consisting of a MAC unit, a register file, a context data register, and PE interconnect control blocks. The main feature of the Proposed architecture is the loop context which enables faster configuration. Also, we propose another area-efficient reconfigurable architecture with improved reconfigurability. The SystemC modeling results show that the proposed architecture can reduce 9 clock cycles of 2D DCT compared to existing architectures.

• Journal of Power Electronics
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• 제18권4호
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.