• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.2
• /
• pp.379-385
• /
• 2015

This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.66 no.12
• /
• pp.1792-1798
• /
• 2017

Event Data Recorder(Car Black-Box) with WiFi dongle have been released, and the platform of the majority is the Linux platform. This is because the platform development is possible in little investment cost by reducing the source licensing costs by taking advantage of the open source. But utilizing Linux platform has the limitations of boot-up time and consuming processing power due to the limitation of battery capacity, to be cost-competitive to minimize the use of memory. In this paper, the real-time operating system(RTOS) is utilized to optimize these portions. MP4 encoder and Muxer are developed to be about ten seconds boot up and minimized memory. It has the advantages of operating at lower power consumption than the Linux utilizing WiFi dongle. Utilizing a WiFi dongle is to provide a progressive download feature on smart phones to lower product prices. But RTOS has the weakness in WiFi. Porting TCP /IP, Web and DHCP server and combination with the USB OTG Host interface by implementing the protocol stack are developed for WiFi. And also SPI NOR flash memory is utilized for faster boot time and cost reductions, low processing power to be consume. As the results, the developed proved the 10 seconds booting time, 24 frame rate/sec. and 10% lower power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.8C
• /
• pp.575-582
• /
• 2008

In this paper we described the process and the results of real-time implementation of G.729.1 wideband speech codec which is standardized in SG15 of ITU-T. To apply the codec on ARM926EJ-S(R) processor core. we transformed some parts of the codec C program including basic operations and arithmetic functions into assembly language to operate the codec in real-time. G.729.1 is the standard wideband speech codec of ITU-T having variable bit rates of $8{\sim}32kbps$ and inputs quantized 16 bits PCM signal per sample at the rate of 8kHz or 16kHz sampling. This codec is interoperable with the G.729 and G.729A and the bandwidth extended wideband($50{\sim}7,000Hz$) version of existing narrowband($300{\sim}3,400Hz$) codec to enhance voice quality. The implemented G.729.1 wideband speech codec has the complexity of 31.2 MCPS for encoder and 22.8 MCPS for decoder and the execution time of the codec takes 11.5ms total on the target with 6.75ms and 4.76ms respectively. Also this codec was tested bit by bit exactly against all set of test vectors provided by ITU-T and passed all the test vectors. Besides the codec operated well on the Internet phone in real-time.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.6C
• /
• pp.865-873
• /
• 2004

MPEG-2 Advanced Audio Coding(AAC) is widely used in the multi-channel audio compression standards. And it combines hi인-resolution filter bank prediction techniques, and Huffman coding algorithm to achieve the broadcast-quality audio level at very low data rates. The forward and inverse modified discrete transforms which are operated in the encoder and the decoder of the filter bank need many computations. In this paper, we propose suitable recursive structure at IMDCT processing for MPEG-2 AAC real-time decoder. We confirm the memory, the computation speed and complexity of the proposed structure.

• Proceedings of the IEEK Conference
• /
• 2001.09a
• /
• pp.33-36
• /
• 2001

멀티 미디어 기술의 총아라고 불리는 차세대 디지털 방송의 핵심적인 기술인 MPEG-2 표준은 주로 방송용에 적합한 고화질 부호화가 목표였다. 1.5Mbps 이하의 저비트율, 즉 보다 고압축률의 부호화 방식에는 대응하고 있지 않았다. MPEG-4 표준 기술은 방송, 통신, 및 컴퓨터 분야에서 앞으로 차기 허용 대역폭이 증가는 하겠지만, 현재의 네트워크 대역폭이 비디오 데이터를 전송하기에는 저대역폭인 상황에서 전송을 위해 새롭게 사용될 멀티미디어 부호화 기술로서 자연 영상뿐만 아니라 그래픽 합성 영상 등 다양한 멀티미디어 정보를 사용자가 대화형으로 쉽게 접근, 편집 처리할 수 있는 기능을 제공한다. 이에 본 논문에서는 향후 다양한 응용 분야에 적용될 MPEG-4 비디오 부호화기를 직접 설계 및 구현함으로써 응용의 가능성을 검증할 수 있는 시스템을 제안한다. 실험결과는 제안한 부호화기의 구조가 국제표준에 근거하여 다양한 응용 제품의 개발에 적합함을 보여 준다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2001.10c
• /
• pp.787-789
• /
• 2001

본 논문에서는 소프트웨어 기반의 실시간 MPEG겨 비디오 부호화기를 제안하였다. MPEG 에서 제공하는 MPEG-4 참조 소프트웨어 비디오 부호화기는 여러 가지 기능이 혼합되어 있는 복잡한 구조를 가지고 있기 때문에 실시간으로 부호화하는 데 많은 어려움이 있다. 이를 PC에서 실시간으로 부호화할 수 있도록 목표를 심플 프로파일로 제한하여 이에 맞도록 구조를 수정하고, 고속 움직임 벡터 예측 알고리즘을 사용하여 움직임 예측시의 계산량을 줄였으며, 실시간으로 부호화할 시에 많은 부하를 주는 부분인 DCT, 움직임 예측 및 보상, 보간 부분을 MMX(MultiMedia Extention) 방법으로 구현하여 계산량과 부하를 줄임으로써 보다 향상된 성능을 제공한다. 기존 부호화기의 부호화 시의 복잡성을 감소시키고 윈도우 환경에서 간단한 조작만으로 부호화를 할 수 있도록 하였다.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.7
• /
• pp.28-37
• /
• 1997

In this paper, we designed a motion estimator for MPEG-2 video coder using VHDL. Motion estimation is indispensable for encoding MPEG 2 video. Motion estimation takes over 50% computation power of video encoding 37 frames per second and is suitable for real-time processing. The number of data accesses for computation is fewer than 2 times compared with that of old one. This makes slower memory module available. We minimize input pins to migrate input data through PEs. This processor can compute various motio estimation modes at one calculation that is supported by MPEG-2 video standard. Also independent control architecture makes this processor a single processor or a sub module in amultimedia chip.

• Transactions of The Korea Fluid Power Systems Society
• /
• v.8 no.2
• /
• pp.1-7
• /
• 2011

An inverted pendulum mounted on a cart and actuated by a hydraulic servo cylinder was designed and built. Position information of the cart was acquired via a potentiometer and a angle of the pendulum was sensed by an incremental encoder. These were collected by a DAQ board and processed through the Real-Time Windows Target software(included in simulink). A simulink graphical program was implemented as a controller of the hydraulic system that governed the motion of the cart in order to maintain vertical balance of the inverted pendulum. The purpose of this study is to develop an electro-hydraulic inverted pendulum system for a modeling and controling the intrinsic unstable system. The simulation results were compared with the experimental and verified.

• 제어로봇시스템학회:학술대회논문집
• /
• 1988.10a
• /
• pp.16-20
• /
• 1988

This paper presents a new algorithm for solving the inverse kinematics in real-time applications. The end-tip movement of each link can be resolved into the basic resolution unit, .DELTA.l, which depends on link length, reduction ratio and resolution of the incremental encoder attached to the joint. When x- and y-axis projection of the end-tip movement are expressed in .DELTA.l unit, projectional increments .DELTA.x and .DELTA.y become -1, 0 or I by truncation. By using the incremental computation with these ternary value and some simple logic rules, a coordinate transformation can be realized. Through this approach, it should be noted that the floating-point arithmetic and the manipulation of trigonometric functions are completely eliminated. This paper demonstrates the proposed method in a parallelogram linkage type, two-link arm.

• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.83-86
• /
• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.