• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.383-393
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• 2000

In shared memory multiprocessor systems, false sharing occurs when several independent data objects, not shared but accessed by different processors, are allocated to the same coherency unit of memory. False sharing is one of the major factors that may degrade the performance of memory coherency protocols. This paper presents a new shared memory allocation scheme to reduce false sharing of parallel applications where master processor controls allocation of all the shared objects. Our scheme allocates the objects to temporary address space for the moment, and actually places each object in the address space of processor that first accesses the object later. Its goal is to allocate independent objects that may have different access patterns to different pages. We use execution-driven simulation of real parallel applications to evaluate the effectiveness of our scheme. Experimental results show that by using our scheme a considerable amount of false sharing faults can be reduced with low overhead.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.6
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• pp.422-426
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• 2007

Personal mobile devices equipped with non-volatile storage such as MP3 player, PMP, cellular phone, and USB memory require safety for the stored data on the devices. One of the safety requirements is secure deletion, which is removing stored data completely so that the data can not be restored illegally. In this paper, we study how to design the secure deletion on Flash memory, commonly used as storage media for mobile devices. We consider two possible secure deletion policy, named zero-overwrite and garbage-collection respectively, and analyze how each policy affects the performance of Flash memory file systems. Then, we propose an adaptive file deletion scheme that exploits the merits of the two possible policies. Specifically, the proposed scheme applies the zero-overwrite policy for small files, whereas it employs the garbage-collection policy for large files. Real implementation experiments show that the scheme is not only secure but also efficient.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.61-68
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• 2007

Two experiments examined the visual memory distortion by presenting 170 subjects with wide-angle views of four scenes on monitor screen. Retention interval of 0, 1 and 48 hours tested in reproduction and recognition experiment. The results of reproduction showed that the subjects tend to magnify the foreground and background of scenes compared to the real input (scene) for all retention intervals. The viewers recognized mure wide-angle views for the same scenes at the retention interval of 1 and 48 hours. These results demonstrated boundary extension is not a robust and unidirectional phenomenon but boundary contraction can be occurred with wide-angle views. The results also suggested that boundary contraction is the product of the activation of a memory schema hypothesis: In memory the representation moves toward a prototypical view and prototypical object size.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.101-121
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• 2010

This paper presents an intelligent prefetching technique that significantly improves performance of hybrid fash-disk storage, a combination of flash memory and hard disk. Since flash memory embedded in a hybrid device is much faster than hard disk in terms of I/O operations, it can be utilized as a 'cache' space to improve system performance. The basic strategy for prefetching is to utilize sequential pattern mining, with which we can extract the access patterns of objects from historical access sequences. We use two techniques for enhancing the performance of hybrid storage with prefetching. One of them is to modify a FAST algorithm for mapping the flash memory. The other is to extend the unit of prefetching to a block level as well as a file level for effectively utilizing flash memory space. For evaluating the proposed technique, we perform the experiments using the synthetic data and real UCC data, and prove the usability of our technique.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.80-88
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• 2002

Visual media(image, graphic, and video) processing poses challenge from several perpectives, specifically from the point of view of real-time implementation and scalability. There have been several approaches to obtain speedups to meet the computing demands in multimedia processing ranging from media processors to special purpose implementations. A variety of parallel processing strategies are adopted in these implementations in order to achieve the required speedups. We have investigated a parallel processing system for improving the processing speed o f visual media related applications. The parallel processing system we proposed is similar to a pipelined memory stystem(MAMS). The multi-access memory system is made up of m memory modules and a memory controller to perform parallel memory access with a variety of combinations of 1${\times}$pq, pq${\times}$1, and p${\times}$q subarray, which improves both cost and complexity of control. Facial recognition, Phong shading, and automatic segmentation of moving object in image sequences are some that have been applied to the parallel processing system and resulted in faithful processing speed. This paper describes the parallel processing systems for the speedup and its utilization to three time-consuming applications.

• The Journal of the Korea Contents Association
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• v.13 no.9
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• pp.28-38
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• 2013

During the past decades, the B+-tree has been most widely used as an index file structure for disk-resident databases. For the disk based B+-tree, a node update can be cheaply performed just by modifying its associated disk page in place. However, in case that the B+-tree is stored on flash memory, the traditional algorithms of the B+-tree come to be useless due to the prohibitive cost of in-place updates on flash memory. For this reason, the earlier schemes for flash memory B+-trees usually take an approach that saves B+-tree changes from real-time updates into extra temporary storage. Although that approach can easily prevent frequent in-place updates in the B+-tree, it can suffer from a waste of storage space and prolonged search times. Particularly, it is not allowable to process range searches on the leaf node level. To resolve such problems, we devise a new scheme in which the leaf nodes and their parent node are stored together in a single flash block, called the p-node block.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.65-70
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• 2022

As fast storage has become popular, the memory management system designed for hard disks needs to be reconsidered. In this paper, we observe that memory access latency is sensitive to the page size when fast storage is adopted. We find the reason from the TLB miss rate, which has the increased impact on the memory access latency in comparison with the page fault rate, and there is trade-off between the TLB miss rate and the page fault rate as the page size is varied. To handle such situations, we model the page fault rate and the TLB miss rate accurately as a function of the page size. Specifically, we show that the power fit and the exponential fit with two terms are appropriate for fitting the TLB miss rate and the page fault rate, respectively. We validate the effectiveness of our model by comparing the estimated values from the model and real values.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.443-445
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• 1990

In this paper, a high speed graphic processor module with a real-time processing capability is proposed, where the module is design to be compatible to the standard VME bus and consists of TMS34010 Graphic processor, TMS44C251 frame buffer, 512KB system memory and BT101 digital to analog converter. The proposed graphic module is implemented and tested in real-time via experiments with an integrated system with other VME modules.

• Journal of the Ergonomics Society of Korea
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• v.23 no.3
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• pp.73-88
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• 2004

This study was contrived Hierarchical Information Search (HIS) model. HIS model is based on a “cognitive process” in which model, comprising basic human information processing mechanize and information interaction. Its process include 3 semantic cognitive processes: Schema-Association LTM, Form Domain, and Alternative Selection. Design methodology consists to elicitate memory, thinking and cognitive response variables. In case study, menu structure of mobile phone was applied. In result, a correlation between predictive error rate and real error rate was .892. and a correlation between selective and real reaction time was .697. This present to suggest a model of how the methodology could be applied to real system design effectively when this was used. HIS model could become one of the most important factors for success of product design. In the perspective, the systemic methodology would contribute to design a quantitative and predictive system.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.3
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• pp.100-107
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• 2002

In this paper, we propose an expert system for electronic interlocking which enhances the safty, efficiency and expanability of the existing system by designing real-time interlocking control based on the interlocking table automatically generated using artificial intelligence approach. The expert system consists of two parts; an interlocking table generation part and a real-time interlocking control part. The former generates automatically the interlocking relationship of all possible routes by searching dynamically the station topology which is obtained from station database. On the other hand, the latter controls the status of station facilities in real-time by applying the generated interlocking relationship to the signal facilities such as signal devices, points, track circuits for a given route. The expert system is implemented in C language which is suitable to implement the interlocking table generation part using the dynamic memory allocation technique. Finally, the effectiveness of the expert system is proved by simulating for the typical station model.