• Journal of Institute of Control, Robotics and Systems
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• v.5 no.1
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• pp.115-121
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• 1999

Advanced digital computer technology enables the computer-based controllers to replace the traditional analog controllers used in factory automations. This replacement, however, brings up the side effects caused by the quantization error and non-real-time execution of control software. This paper describes the structure of real-time simulator and controller that can be used for design and verification of real-time digital controllers. The virtual machine concept adopted by the proposed real-time simulator makes the proposed simulator be independent from the specific hardware platforms. The proposed system can also be used in the loosely coupled distributed environments connected through local area network using real-time message passing algorithm and virtual data table based on the shared memory mechanism.

• International journal of advanced smart convergence
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• v.11 no.1
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• pp.28-35
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• 2022

This paper presents a performance evaluation of real-time Linux for industrial real-time platforms. On industrial platforms, multicore processors are popular due to their work distribution efficiency and cost-effectiveness. Multicore processors, however, are not designed for applications with real-time constraints, and their performance capabilities depend on their core configurations. In order to assess the feasibility of a multicore processor for real-time applications, we conduct a performance evaluation of a general processor and a low-power processor to provide an experimental environment of real-time Linux on both Xenomai and RT-preempt considering the multicore configuration. The real-time performance is evaluated through scheduling latency and in an environment with loads on the CPU, memory, and network to consider an actual situation. The results show a difference between a low-power and a general-purpose processor, but from developer's point of view, it shows that the low-power processor is a proper solution to accommodate low power situations.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.486-490
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• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.23-33
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• 1996

The exploitation of locality of reference in shared memory NUMA multiprocessors is one of the improtant problems in parallel processing today. In this paper, we propose a revised hardeare reference counter to help operating system to manage locality. In contrast to the previous one, the value of counter can abe adjusted dynamically and periodically to adapt the page replication policy to the various memory reference patterns of processors. We use execution-driven simulation of real applications to evaluate the effectiveness of our adjustable DELAY counter. Our main conclusijon is that by using the adjustable DELAY counter the t normalized average memory access costs and the variance of them become smaller for most applications than the previous one and more robust memory management policies can be provided for the operating systems.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2204-2218
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• 2000

This paper proposes a dynamic storage allocation algorithm, QHF(quick-half-fit) for real-time systems. The proposed algorithm manages a free block list per each worked size for memory requests of small size, and a free block list per each power of 2 size for memory requests of large size. This algorithms uses the exact-fit policy for small sie requests and provides high memory utilization. The proposed algorithm also has the time complexity O(I) and enables us to easily estimate the worst case execution time (WCET). In order to confirm efficiency of the proposed algorithm, we compare he memory utilization of proposed algorithm with that of half-fit and binary buddy system that have also time complexity O(I). The simulation result shows that the proposed algorithm guarantees the constant WCET regardless of the system memory size and provides lower fragmentation ratio and allocation failure ratio thant other two algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.667-677
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• 1990

In this paper, optical inplementation of the Hopfield neural network model for two-dimensinal associative memory is described For the real-time processing of two-dimensional images, the commercial LCTVs are used as a memory mask and an input spatical light modulator. A 4-D memory matrix is realized with a 2-D mask of a matrix arrangement and the inner-products between arbitrary input pattern and memory matrix are carried out by using the multifocus hololens. The output image is then electronically thresholded and fed back to the input of the associative memory system by 2-D CCd camera. From the good experimental results for the high error correction capability, the proposed system can be applied to practical pattern recognition and machine vision systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5A
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• pp.545-553
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• 2004

Expansion of network environment and multimedia demand universality of application service as HDTV, etc. During these processes, it is essential to process multimedia in real time in the wireless communication system based on mobile phone network and in the wire communication system due to fiber cable and xDSL. So, in this Paper the optimal memory allocation algorithm combines the merit of huffman encoding which is superior in simultaneous decoding ability and lempel-ziv that is distinguished in execution of compress is proposed to improve the channel transmission rate and processing speed in the compressing procedure and is verified in the entropy encoder of HDTV. Because the entropy encoder system using proposed optimal memory allocation algorithm has memory saturation prevention we confirms that the compressing ratio for moving pictures is superior than Huffman encoding and LZW.

• The KIPS Transactions:PartB
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• v.10B no.5
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• pp.575-578
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• 2003

SPIHT algorithm is a wavelet based fast and effective technique for image compression. It uses a list structure to store status information which is generated during set-partitioning of zero-tree. Usually, this requires lots of additional memory depending on how high the bit-rate is. Therefore, in this paper, we propose a new technique called MZP-DFS, which needs no additional memory when running SPIHT algorithm. It traverses a spatial-tree according to DFS and eliminates additional memory as it uses test-functions for encoding and LSB bits of coefficients for decoding respectively. This method yields nearly the same performance as SPIHT. This may be desirable in hardware implementation because no additional memory is required. Moreover. it exploits parallelism to process each spatial-tree that it can be applied well in real-time image compression.

• Earthquakes and Structures
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• v.23 no.5
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• pp.431-444
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• 2022

The unique thermomechanical properties of shape memory alloys (SMAs) make it a versatile material for strengthening and repairing structures. In particular, several research studies have already demonstrated the effectiveness of using the heat activated shape memory effect of nickel-titanium (Ni-Ti) based SMAs to actively confine concrete members. Despite the proven effectiveness and wide commercial availability of Ni-Ti SMAs, however, their high cost remains a major obstacle for applications in real structural engineering projects. In this study, the shape memory effect of a new, much more economical iron-based SMA (Fe-SMA) is characterized and the compressive behavior of concrete confined with Fe-SMA strips is investigated. Tests showed the Fe-SMA strips used in this study are capable of developing high levels of recovery stress and can be easily formed into hoops to provide effective active and passive confining pressure to concrete members. Compared to concrete cylinders confined with conventional carbon fiber-reinforced polymer (CFRP) composites, Fe-SMA confinement yielded significantly higher compressive deformation capacity and residual strength. Overall, the compressive behavior of Fe-SMA confined concrete was comparable to that of Ni-Ti SMA confined concrete. This study clearly shows the potential for Fe-SMA as a robust and cost-effective strengthening solution for concrete structures and opens possibilities for more practical applications.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3037-3039
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• 2005

The AIS(Automatic Identification System) transmits the position of ships and other information to prevent accidents which could occur in the sea. It has to be developed SOTDMA(Self-Organized Time Division Multiple Access) Algorithm which is important on wireless communication method for the AIS because It is based on ITU(International Telecommunication Union) M.1371-1 of the international standard therefore, we need to develop a performance evaluation simulator efficiently to develop and analyze SOTDMA Algorithm. this paper shows the method of designing it. Real ships access The VHF maritime mobile band but in this performance evaluation simulator several ship objects access the shared memory. Real ships are designed as the object and the wireless communication channel is designed as the shared memory. The ships apply for real virtual data which got from assistance hardware and The SOTDMA Algorithm driving state verifies the performance evaluation simulator by IEC(International Electrotechnical commission) 61993-2. After verifying results the performance evaluation simulator is correctly satisfied with IEC 61993-2. So we expect that it helps not only the AIS technology developed but also verify new SOTDMA Algorithm