• Journal of the Korean Ceramic Society
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• v.31 no.10
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• pp.1115-1122
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• 1994

ZT/PZT/ZT multi-layered thin films were deposited on silicon substrate by co-sputtering method for FEMFET device application. Effects of Pb/(Zr+Ti) ratio, films thickness, annealing conditions and substrate temperature on the ferroelectric behavior of the multi-layered films were studied. The best memory device characteristics with leakage current of 2$\times$10-8 A/$\textrm{cm}^2$ and breakdown field of about 1 MV/cm could be obtained with ZT(250 $\AA$) / PZT(1000 $\AA$)/ZT(750 $\AA$) multi-layered thin film deposited at 35$0^{\circ}C$ and post-annealed at $700^{\circ}C$ for 120 sec by RTA(Rapid Thermal Annealing).

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1469-1472
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• 2006

We investigated the electrical and optical properties of ZnO:Al thin films as a function of the thermal process conditions. The film was prepared by RF magnetron sputtering followed by annealing in a box furnace in air. An ZnO:Al (98:2) alloy with the purity of 99.99% (3 inch diameter) was used as the target material. The electrical properties of the transparent electrode, exhibited surface oxidation as a result of rapid oxygen absorption with increasing annealing temperature. The processed ZnO:Al films and commercial ITO(indium-tin-oxide) were applied to an OLED stack to investigate the current density and luminescence efficiency. The efficiency of the device using the ZnO:Al electrode was higher than that from the device using the ITO electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.2
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• pp.123-129
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• 2001

The optimal high temperature processing conditions for the formation of Ohmic contact of Ti/Al/Pt/Au multiple layers were established for the fabrication of n$^{+}$-GaN/AlGaN/GaN HFET device. Contact resistivity as low as 3.4x10$^{-6}$ ohm-$\textrm{cm}^2$ was achieved by the annealing of the sample at 100$0^{\circ}C$ for 10 sec. using the RTA (Rapid Thermal Annealing) system. The fabricated HFET (Heterostructure Field Effect Transistor) with a structure of n'-GaN/undoped AlGaN/undoped GaN exhibited a low knee voltage of 3.5 V and a maximum source-drain current density of 180 mA/mm at Vg=0V.V.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.9
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• pp.1381-1387
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• 1989

For the fabrication of ohmic contact to p-type GaAs, In Liquid Metal Ions were implanted into p-type GaAs (Zn:1.5x10**19/cm**3). After the samples were processed by Infrared rapid thermal annealing (IRTA0 or Furance Annealing (FA), I-V and specific contact contact resistivity were measured. Specific contact resistivity was found to be 1.7x10**-5 \ulcorner-cm\ulcornerin IRTA 750\ulcorner, 10 sec annealed sample. The surface characteristics of the samples were investigated with SEM, RHEED, AES. From these results we can know that implanted In ions were formed mixing layer of InAs at the surface.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.307-309
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• 2005

We investigated light absorption layer effect on metal-induced lateral crystallization (MILC) growth rate and MILC thin films transistors (TFTs). As annealing method, we used scanning-rapid thermal annealing (RTA). MILC growth rate which was crystallized by light absorption layer and using scanning-RTA was 3 times than normal MILC which was without light absorption layer growth rate. Also we compared MILC TFTs characteristics which were combined to light absorption layer with conventional MILC TFTs. After scanning-RTA process, MILC-TFTs which were with light absorption layer were superior to conventional MILC-TFTs. With this new MILC-TFTs structure, we could reduced crystallization time and obtain good electrical properties.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.555-562
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• 1990

Alloyed ohmic contact properties of Au-Zn/Au, Au-Be/Au,Au-Zn/Cr/Au, and Au-Be/Cr/Au metal system to p-InP were investigated. Optimum alloying conditions were obtained at the annealing temperature of 425\ulcorner for all the metal systems using a rapid thermal annealing system. Surface AES analysis and auger depth profiling were done for each metal system annealed at the optimum conditions. Outdiffusions of In and P from the InP substrate were found in the metal systems without Cr intermediate layer. Also, small amount of In. P and Cr were detected at the surface in the case of Au-Zn/Cr/Au system, while there were occured no outdiffusion of In, P, and Cr for Au-Be/Cr/Au system. The best surface morpholoty and specific contact resistivity of 4.5x 10**-5 \ulcornercm\ulcornerhave been obtained in this Au-Be/Cr/Au material system alloyed at 425\ulcorner for 60 second.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.553-556
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• 2009

We investigated an application of supramolecular protein, and demonstrated the metal induced lateral crystallization utilizing ferritins with Ni nanoparticles, named the "bio-nano-crystallization". So far, this method has required long time, because of this method condition based on the conventional solid phase crystallization. In this study, we applied the pulsed rapid thermal annealing to bio-nanocrystallization. As a result, we succeeded in the crystallization for a short time. We found that the TFTs characteristics were improved with decrease metal impieties in poly-Si thin films by this method.

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.62-63
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• 1993

Salicide(Self-aligned) CoSi$_2$의 형성을 알아보기 위하여, 단결정 실리콘 기판내에 불순물 주입에 따른 실리사이드의 형성영향을 알아보는, As,BF$_2$를 주입 한 시편과, 코발트와 SiO$_2$를 증착한 시편을 준비하였다. RF sputtering 방식으로 각각의 기판위에 코발트를 증착 한 후 Rapid Thermal Annealing(RTA) 온도 400-100$0^{\circ}C$영역에서 20초 동안 열처리 하였다. RTA 온도 80$0^{\circ}C$에서 비저항이 약 18$\mu$$\Omega$-cm정도의 CoSi$_2$를 형성 시켰으며 SEM 과 $\alpha$-step 으로 확인된 Si 기판과 코발트 실리사이드의 계면 roughness 및 surface roughness는 우수하였고, CoSi$_2$의 두께 증가에 따른 실리콘 소모량의 증가에 따라 기판내에 있던 As,BF$_2$ 이온들이 실리사이드내로 재분포 되는 현상을 보였다.CoSi$_2$/Si 계면간의 열적안정성은 $N_2$분위기로 30분간 Furnace Annealing 온도 100$0^{\circ}C$까지 CoSi$_2$의 응집화 현상이 일어나지 않았다.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.546-548
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• 1987

We have studied 1iquid phase regrowth of phosphorus ion implanted silicon films on insulator (SOI) by rapid thermal annealing (RTA) method. Many twin boundaries were observed on the regrown silicon layer and mobility of the layer was increased from $14\;cm^2/v.sec$ to $38\;cm^2/v.sec$ after annealing at $1150^{\circ}C$ for 15 sec.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1990.10a
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• pp.81-85
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• 1990

$WSi_{x}$ film deposited on p+ polysilicon by low pressure chemical vapor deposition method were annealed by rapid thermal process, their properties have been investigated by measurements of electrical resistivity and Hall voltage and by analyses of phases and microstructure using X-ray diffraction and SEM technique. The electrical resistivity of the polycides consisting of the tungsten silicide and the p+ polysilicon decreases with the increase in annealing temperature due probably to the increase in grain size. unlike the polycides consisting of the $WSi_{x}$ and n+ polysilicon, however, the Hall voltage of the polycides consisting of $WSi_{x}$ and p+ polysilicon were positive for all specimens annealed as well as the as-deposited one, indicating the majority carrier in $WSi_{x}$. is hole and is independent of the annealing.