• 한국전기전자재료학회논문지
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• 제36권6호
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• pp.582-587
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• 2023

The effects of the annealing temperature on the structural, morphological, and luminescent properties of SrWO₄:Sm³⁺ thin films grown on quartz substrates by radio-frequency magnetron sputtering were investigated. The thin films were annealed at various annealing temperatures for 20 min in a rapid thermal annealer after growing the thin films. The experimental results showed that the annealing temperature has a significant effect on the properties of the SrWO₄:Sm³⁺ thin films. The crystal structure of the as-grown SrWO₄:Sm³⁺ thin films was transformed from amorphous to crystalline after annealing at 800℃. The preferred orientation along (112) plane and a significant increase in average grain size by 820 nm were observed with increasing the annealing temperature. The average optical transmittance in the wavelength range of 500~1,100 nm was decreased from 72.0% at 800℃ to 44.2% at an annealing temperature of 1,000℃, where the highest value in the photoluminescence intensity was obtained. In addition to the red-shift of absorption edge, a higher annealing temperature caused the optical band gap energy of the SrWO₄:Sm³⁺ thin films to fall rapidly. These results suggest that the structural, morphological, and luminescent properties of SrWO₄:Sm³⁺ thin films can be controlled by varying annealing temperature.

• 한국진공학회지
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• 제10권3호
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• pp.335-340
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• 2001

RF마그네트론 스퍼터링법으로 사파이어 기판 위에 Ga을 1 wt% 첨가한 ZnO 박막(GZO)을 기판온도 $550^{\circ}C$에서 성장시켜 다결정 박막을 제조하였다. 이러한 박막은 불충분한 전기적 특성이나 PL(Photoluminescence) 특성을 보이고 있다. 이러한 전하농도, 이동도 그리고 PL특성 등과 같은 전기적 광학적 특성을 향상시키고자 질소분위기하에서 RTA(Rapid Thermal Annealing) 법으로 $800^{\circ}C$와 $900^{\circ}C$에서 각각 3분씩 후열처리 하였다. RTA법으로 후열처리한 GZO박막의 비저항은 $2.6\times10^{-4}\Omega$/cm 였으며 전자농도와 이동도는 각각 $3.9\times10^{20}/\textrm{cm}^3$과 60 $\textrm{cm}^2$/V.s 였다. 이러한 물리적 성질들의 향상은 열처리시 원자 크기가 비슷한 도핑된 Ga 원자들이 일부 휘발되는 Zn 빈자리로 치환하면서 침입자리 보다는 치환자리로의 전이에 기인한 것으로 생각된다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1343_1344
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• 2009

In this work, transparent conducting Al-doped zinc oxide (AZO) films were prepared on Corning glass substrate by RF magnetron sputtering using an Al-doped ZnO target (Al: 2 wt.%) at room temperature and all films were deposited with athickness of 150 nm. We investigated the effects of the post-annealing temperature and the annealing ambient on structural, electrical and optical properties of AZO films. The films were annealed at temperatures ranging from 300 to $500^{\circ}C$ in steps of $100^{\circ}C$ using rapid thermal annealing equipment in oxygen. The thickness of the film was observed by field emission scanning electron microscopy (FE-SEM) and grain size was calculated from the XRD spectra using the Scherrer equation and their electrical properties were investigated using a hole measurement and the reflectance of AZO films was investigated by UV-VIS spectrometry.

• 전자공학회논문지A
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• 제30A권8호
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• pp.42-48
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• 1993

Ar ions were implanted at 1 MeV into (100)Cz Si wafers with dose of 1 * 10$^{15}$ ions/cm$^{2}$. Damage induced by high energy implantation and its annealing behavior during rapid thermal annealing for 10sec at temperatures from 550 to 1100${\circ}C$ were investigated by crosssection transmission electron microscopy study. It can be clearly seen from the observation that the SPE(Solid Phase Epitaxy) regrowth of the buried amorphous layer induced by ion implantation proceeds from both upper and lower amorphous/crystalline (a/c) interfaces, and the activation energy for SPE from interfaces were both 1.43eV. Misfit dislocation where two interfaces met was formed and it coalesced into the hair pin dislocation in the upper regrown region. At the higher temperature after annealing out of the misfit dislocation, hair pin dislocations showed considerable drop in its bandwidth. However, they were not disappeared even at the temperature 1100${\circ}C$ with the end of range dislocation loops which were formed at the original lower a/c interface.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.329-332
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• 1999

In this paper, BST((Bao.&o,dTi0:3) thin films were deposited by the rf magnetron sputtering method on Pt/$SiO_2$/Si substrate. Pt, $RuO_2$, Ag, Cu films for the formation of top electrode were deposited on BST thm films. And then Top Electrodes/BST/Pt capacitors were annealed with rapid thermal annealing(RTA) at various temperature. We have investigated effect of post-annealing on the electrical properties such as dielectric constant and leakage current of the capacitors. It was found that electrical properties of the capacitors were greatly depended on the annealing temperatures as well as the materials of top electrodes. In BST thin films with Pt top electrode was annealed at $700^{\circ}C$. the dielectric constant was measured to the value of 346 at l[kHzl and the leakage current was obtained to the value of $8.76\times10^8$[A/$\textrm{cm}^2$] at the forward bias of 2[V].

• 전자공학회논문지A
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• 제31A권8호
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• pp.91-99
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• 1994

Damage induced by Si ion implantation and its annealing behavior during rapid thermal annealing were investigated by cross-sectional TEM (transmission electron microscopy) and RB ( Rutherford backscattering) spectrum. 150keV and 50keV Si ions were implanted in Si (100) at room temperature with doses of 2${\times}10^{15}cm^{-2}$. And 100keV Si ions were implanted in Si with doses from 1${\times}10^{14}cm^{-2}$. A variety of damage structures were generated by Si ion implantation such as continuous amorphous layer extending to the surface buried amorphous layer and damage clusters. Damage clusters are annealed out at the lower annealing temperature of 550 $^{\circ}C$. However, event at the temperature of 110$0^{\circ}C$ end of range loops remain in the original lower amorphous/crystal interface in the case of continuous and buried amorphous layer formation. Extended defects in the shape of zipper dislocations are also observed at the middle of the recrystallized region in the buried amorphous layer.

• 한국세라믹학회지
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• 제37권8호
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• pp.731-738
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• 2000

KLN(K3Li2Nb5O15) has attracted a great deal of attention for their potential usefulness in piezoelectric, electro-optic, nonlinear optic, and pyroelectirc devices. Especially, the KLN single crystal has been studied in the field of optics and electronics. However it is hard to produce good quality single crystals due to the crack propagation during crystal growing. One of the solutions of this problem is prepartion of thin film. But the intensive study has not been conducted so far. In this study, after the KLN thin film were prepared by R.F. magnetron Sputtering method on SiO2/Si substrate, the post-annealing methods of RTA(rapid thermal annealin) and IPA(insitu post annealing) were employed. The deposition condition of KLN thin film was RF power(100 W), Working pressure(100 mtorr). The commonness of both RAT and IPA was that the higher were deposition and post annealing temperature, the higher was the intensity of XRD but the less surface roughness. The difference of post-annealing methods affected XRD phase and surface condition very much. And in IPA process, the influence of O2 had much effect on the formation of KLN phase.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.3-6
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• 2003

This paper describes the interface stability of Ta-Mo alloy metal on $SiO_2$ Alloy was formed by co-sputtering method, and the alloy composition was varied by controlling Ta and Mo sputtering power. When the atomic composition of Ta was about 91%, the measured work function was 4.2eV that is suitable for NMOS gate. To identify interface stability between Ta-Mo alloy metal and $SiO_2$, C-V, FE-SEM(Field Emission-SEM), and XRD(X-ray diffraction) were performed on the samples annealed with rapid thermal processor between $600^{\circ}C$ and $900^{\circ}C$. Even after $900^{\circ}C$ rapid thermal annealing, excellent interface stability and electrical properties were observed. Also, thermodynamic analysis was studied to compare with experimental results.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2001년도 제21회 학술발표회 초록집
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• pp.66-66
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• 2001