• KIEE International Transactions on Electrophysics and Applications
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• v.12C no.4
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• pp.208-213
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• 2002

The present study describe the electrical performance of amorphous T $a_2$ $O_{5-X}$ fabricated on the buffer layers Ti and Ti $O_2$. T $a_2$ $O_{5-X}$ thin films were grown on the Ti and Ti $O_2$ layers as a capacitor layer using reactive sputtering method. The X-ray pattern analysis indicated that the two as-deposited films were amorphous and the amorphous state was kept stable on the RTA(rapid thermal annealing) at even $700^{\circ}C$. Measurements of dielectric properties of the reactive sputtered T $a_2$ $O_{5-X}$ thin films fabricated in two simple MIS(metal insulator semiconductor), structures, (Cu/T $a_2$ $O_{5}$ Ti/Si and CuT $a_2$ $O_{5}$ Ti $O_2$Si) show that the amorphous T $a_2$ $O_{5}$ grown on Ti showed high dielectric constant (23～39) and high leakage current density(10$^{-3}$ ～10$^{-4}$ (A/$\textrm{cm}^2$)), whereas relatively low dielectric constant (～15) and tow leakage current density(10$^{-9}$ ～10$^{-10}$ (A/$\textrm{cm}^2$)) were observed in the amorphous T $a_2$ $O_{5}$ deposited on the Ti $O_2$ layer. The electrical behaviors of the T $a_2$ $O^{5}$ thin films were attributed to the contribution of Ti- $O_2$ and the compositionally gradient Ta-Ti-0, being the low dielectric layer and high leakage current barrier. In additional, The T $a_2$ $O_{5}$ Ti $O_2$ thin films exhibited dominant conduction mechanism contributed by the Poole-Frenkel emission at high electric field. In the case of T $a_2$ $O_{5}$ Ti $O_2$ thin films were related to the diffusion of Ta, Ti and O, followed by the creation of vacancies, in the rapid thermal treated thin films.films.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.16-22
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• 2008

We fabricated thermally-evaporated 10 nm-Ni/30 nm and 70 nm Poly-Si/200 nm-$SiO_2/Si$ structures to investigate the thermal stability of nickel silicides formed by rapid thermal annealing(RTA) of the temperature of $300{\sim}1100^{\circ}C$ for 40 seconds. We employed for a four-point tester, field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), high resolution X-ray diffraction(HRIXRD), and scanning probe microscope(SPM) in order to examine the sheet resistance, in-plane microstructure, cross-sectional microstructure evolution, phase transformation, and surface roughness, respectively. The silicide on 30 nm polysilicon substrate was stable at temperature up to $900^{\circ}C$, while the one on 70 nm substrate showed the conventional $NiSi_2$ transformation temperature of $700^{\circ}C$. The HRXRD result also supported the existence of NiSi-phase up to $900^{\circ}C$ for the Ni silicide on the 30 nm polysilicon substrate. FE-SEM and TEM confirmed that 40 nm thick uniform silicide layer and island-like agglomerated silicide phase of $1{\mu}m$ pitch without residual polysilicon were formed on 30 nm polysilicon substrate at $700^{\circ}C\;and\;1000^{\circ}C$, respectively. All silicides were nonuniform and formed on top of the residual polysilicon for 70 nm polysilicon substrates. Through SPM analysis, we confirmed the surface roughness was below 17 nm, which implied the advantage on FUSI gate of CMOS process. Our results imply that we may tune the thermal stability of nickel monosilicide by reducing the height of polysilicon gate.

• Korean Journal of Materials Research
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• v.4 no.8
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• pp.855-860
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• 1994

Ta-silicide films in polycide structure were prepared by rapid thermal annealing of sputtered Ta film on poly-Si and doped poly-Si. Effects of phosphorus on Ta-silicide formation were investigated. Independent of the ion dose($1 \times 10^{13}\to 5 \times 10^{15}$/ions/$\textrm{cm}^2$), Ta-silicide phases were formed at $800^{\circ}C$ and stabilized above $1000^{\circ}C$. From the result of XRD at $800^{\circ}C$ and $900^{\circ}C$, however, it was indicated that the more the doping concentration the weaker the intensity of Ta-silicide phases. Furthermore, the observation of SEM revealed that the increase of the doping concentration retarded silicidation. As the temperature increased, the dopant effect was weakened gradually and almost disappeared at $1000^{\circ}C$. Therefore the variation of the ion dose from ($1 \times 10^{13}\to 5 \times 10^{15}$/ions/$\textrm{cm}^2$) did not greatly affect the formation of Ta-silicide at high temperatures but retarded slightly the silicidation at low temperatures.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.129-129
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• 2016

Graphene, as a single layer of $sp^2$-bonded carbon atoms packed into a 2D honeycomb crystal lattice, has attracted much attention due to its outstanding properties. In order to synthesize high quality graphene, transition metals, such as nickel and copper, have been widely employed as catalysts, which needs transfer to desired substrates for various applications. However, the transfer steps are not only complicated but also inevitably induce defects, impurities, wrinkles, and cracks of graphene. Furthermore, the direct synthesis of graphene on dielectric surfaces has still been a premature field for practical applications. Therefore, cost effective and concise methods for transfer-free graphene are essentially required for commercialization. Here, we report a facile transfer-free graphene synthesis method through nickel and carbon co-deposited layer. In order to fabricate 100 nm thick NiC layer on the top of $SiO_2/Si$ substrates, DC reactive magnetron sputtering was performed at a gas pressure of 2 mTorr with various Ar : $CH_4$ gas flow ratio and the 200 W DC input power was applied to a Ni target at room temperature. Then, the sample was annealed under 200 sccm Ar flow and pressure of 1 Torr at $1000^{\circ}C$ for 4 min employing a rapid thermal annealing (RTA) equipment. During the RTA process, the carbon atoms diffused through the NiC layer and deposited on both sides of the NiC layer to form graphene upon cooling. The remained NiC layer was removed by using a 0.5 M $FeCl_3$ aqueous solution, and graphene was then directly obtained on $SiO_2/Si$ without any transfer process. In order to confirm the quality of resulted graphene layer, Raman spectroscopy was implemented. Raman mapping revealed that the resulted graphene was at high quality with low degree of $sp^3$-type structural defects. Additionally, sheet resistance and transmittance of the produced graphene were analyzed by a four-point probe method and UV-vis spectroscopy, respectively. This facile non-transfer process would consequently facilitate the future graphene research and industrial applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.771-780
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• 2001

It is indispensable to use the process and device simulation tool in order to analyze accurately the electrical characteristics of ULSI CMOS devices, in addition to developing and manufacturing those devices. The 3D Monte Carlo (MC) simulation result is not efficient for large-area application because of the lack of simulation particles. In this paper is reported a new efficient simulation strategy for 3D MC ion implantation into large-area application using the 3D MC code of TRICSI(TRansport Ions into Crystal Silicon). The strategy is related to our newly proposed split-trajectory method and ion-splitting method(ion-shadowing approach) for 3D large-area application in order to increase the simulation ions, not to sacrifice the simulation accuracy for defects and implanted ions. In addition to our proposed methods, we have developed the cell based 3D interpolation algorithm to feed the 3D MC simulation result into the device simulator and not to diverge the solution of continuous diffusion equations for diffusion and RTA(rapid thermal annealing) after ion implantation. We found that our proposed simulation strategy is very computationally efficient. The increased number of simulation ions is about more than 10 times and the increase of simulation time is not twice compared to the split-trajectory method only.

• Journal of Sensor Science and Technology
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• v.9 no.3
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• pp.242-247
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• 2000

$Pb_{0.99}[(Zr_{0.6}Sn_{0.4})_{0.9}Ti_{0.1}]_{0.98}Nb_{0.02}O_3(PNZST)$ thin films were deposited by RF magnetron sputtering on $(La_{0.5}Sr_{0.5})CoO_3(LSCO)/Pt/Ti/SiO_2/Si$ substrate using a PNZST target with excess PbO of 10 mole%. The thin films deposited at substrate temperature of $500^{\circ}C$, and at RF power of 80W were crystallized to a perovskite phase after rapid thermal annealing(RTA). The thin films annealed at $650^{\circ}C$ for 10 seconds in air exhibited the good structures and electrical properties. The fabricated PNZST capacitor had a remanent polarization value of about $20\;{\mu}C/cm^2$ and coercive field of about 50 kV/cm. The reduction of the polarization after $2.2{\times}10^9$ switching cycles was less than 10%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.851-856
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• 2003

We have investigated the material and electrical properties of $Bi_{4-x}La_xTi_3O_{12}$ (BLT) ferroelectric thin film for ferroelectric nonvolatile memory applications of capacitor type and single transistor type. The 120nm thick BLT films were deposited on $Pt/Ti/SiO_2/Si$ and $SiO_2/Nitride/SiO_2$ (ONO) substrates by the sol-gel spin coating method and were annealed at $700^{\circ}C$. It was observed that the crystallographic orientation of BLT thin films were strongly affected by the excess Bi content and the intermediate rapid thermal annealing (RTA) treatment conditions regardeless of two type substrates. However, the surface microstructure and roughness of BLT films showed dependence of two different type substrates with orientation of (111) plane and amorphous phase. As increase excess Bi content, the crystallographic orientation of the BLT films varied drastically in BLT films and exhibited well-crystallized phase. Also, the conversion of crystallographic orientation at intermediate RTA temperature of above $450^{\circ}C$ started to be observed in BLT thin films with above excess 6.5% Bi content and the rms roughness of films is decreased. We found that the electrical properties of BLT films such as the P-V hysteresis loop and leakage current were effectively modulated by the crystallographic orientations change of thin films.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.131-131
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• 2013

A single-layer graphene has been uniformly grown on a Cu surface at elevated temperatures by thermally processing a poly(methyl methacrylate) (PMMA) film in a rapid thermal annealing (RTA) system under vacuum. The detailed chemistry of the transition from solid-state carbon to graphene on the catalytic Cu surface was investigated by performing in-situ residual gas analysis while PMMA/Cu-foil samples being heated, in conjunction with interrupted growth studies to reconstruct ex-situ the heating process. The data clearly show that the formation of graphene occurs with hydrocarbon molecules vaporized from PMMA, such as methane and/or methyl radicals, as precursors rather than by the direct graphitization of solid-state carbon. We also found that the temperature for vaporizing hydrocarbon molecules from PMMA and the length of time the gaseous hydrocarbon atmosphere is maintained, which are dependent on both the heating temperature profile and the amount of a solid carbon feedstock are the dominant factors to determine the crystalline quality of the resulting graphene film. Under optimal growth conditions, the PMMA-derived graphene was found to have a carrier (hole) mobility as high as ~2,700 cm2V-1s-1 at room temperature, superior to common graphene converted from solid carbon.

• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• Korean Journal of Materials Research
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• v.11 no.10
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• pp.889-894
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• 2001

2wt% $Al_2O_3-doped$ ZnO (AZO) thin films were deposited on sapphire (0001) single crystal substrate by parellel type rf magnetron sputtering at 55$0^{\circ}C$. The as-grown AZO thin films was polycrystalline and showed only broad deep defect-level photoluminescence (PL). In order to examine the change of PL property, AZO thin films were annealed in $N_2$ (N-AZO) and $H_2$ (H-AZO) at the temperature of $600^{\circ}C$~$1000^{\circ}C$ through rapid thermal annealing. After annealed at $800^{\circ}C$, N-AZO shows near band edge emission (NBE) with very small deep-level emission, and then N-AZO annealed at $900^{\circ}C$ shows only sharp NBE with 219 meV FWHM. In Comparison with N-AZO, H-AZO exhibits very interesting PL features. After $600^{\circ}C$ annealing, deep defect-level emission was quire quenched and NBE around 382 nm (3.2 eV) was observed, which can be explained by the $H_2$passivation effect. At elevated temperature, two interesting peaks corresponding to violet (406 nm, 3.05 eV) and blue (436 nm, 2.84 eV) emission was firstly observed in AZO thin films. Moreover, peculiar PL peak around 694 nm (1.78 eV) is also firstly observed in all the H-AZO thin films and this is believed good evidence of hydrogenation of AZO. Based on defect-level scheme calculated by using the full potential linear muffin-tin orbital (FP-LMTO), the emission 3.2 eV, 3.05 eV, 3.84 eV and 1.78 eV of H-AZO are substantially deginated as exciton emission, transition from conduction band maximum to $V_{ Zn},$ from $Zn_i$, to valence band maximum $(V_{BM})$ and from $V_{o} to V_BM}$, respectively.