• Title/Summary/Keyword: ramp generator

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Steady-State and Transient Performance Simulation of a Turboshaft Engine with a Free Power Turbine

  • King, Chang-Duk;Chung, Suk-Choo
    • Journal of Mechanical Science and Technology
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    • v.14 no.11
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    • pp.1296-1304
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    • 2000
  • A program of steady-state and transient performance analysis for a 200kW-class small turboshaft engine with free power turbine was developed. An existing turbojet engine was used for the gas generator of the developed turboshaft engine, which was modified to satisfy performance requirements of this turboshaft engine. To verify the accuracy of steady-state performance program for this engine: the program was applied to the gas turbine test unit of the same type, and the analysis results were compared with experimental results. The developed transient performance analysis program using the CMF (Constant Mass Flow) method was utilized to analyze the cases of step increase and ramp increase of the fuel.

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PLC Aapplication in Exothermic Batch Process (Exothermic Batch 공정의 PLC 응용)

  • 김연태;김영권;임채환
    • 제어로봇시스템학회:학술대회논문집
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    • 1990.10a
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    • pp.639-642
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    • 1990
  • 본 EXOTHERMIC BATCH 공정은 두 개의 FLUID BED REACTOR로 구성되며 여기서 다종의 제품이 생산된다. 각 제품은 그 제품 자체의 특징 온도 패턴을 갖게 되며 허용한계를 벗어나지 않는 제품을 생산하기 위해서는 그 특징 온도 패턴대로 제어되어야 하며 실패할 경우 그 배치를 포기하여야만 한다. 초기의 배치제어시스템에서는 램프 제너레이터(RAMP GENERATOR) 기능이 있는 공기식 계기가 사용되었으며 제품을 변경하기 위해서는 각 제품마다 일일이 그 특징 패턴을 수동으로 입력시켜 주어야만 했다. 이 과정에서 한 개의 파라미터를 실수하면 사용할 수 없는 제품이 된다. 다종 제품의 화학공정에서는 품질과 생산량 향상에 의한 이득 증대에 그 목표를 두고 있으며, 이와 같은 목표를 달성하기 위한 해결책은 운전자의 개입을 감소시켜주는 제어시스템으로 개선하는 것이었다. 본 논문에서는 배치공정에 있어서의 프로그래머블 콘트롤러(PROGRAMMABLE CONTROLLER)의 응용에 관하여 논술하고자 한다.

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High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs

  • Lee, Junan;Huang, Qiwei;Kim, Kiwoon;Kim, Kyunghoon;Burm, Jinwook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.1
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    • pp.22-28
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    • 2015
  • This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.

A Design of A Multistandard Digital Video Encoder using a Pipelined Architecture

  • Oh, Seung-Ho;Park, Han-Jun;Kwon, Sung-Woo;Lee, Moon-Key
    • Journal of Electrical Engineering and information Science
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    • v.2 no.5
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    • pp.9-16
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    • 1997
  • This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals, It also processes he PAL-plus video signal which is now popular in Europe. The encoder consists of five major building functions which are letter-box converter, color space converter, digital filters, color modulator and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance signal-to-noise ratio of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs re luminance(Y), chrominance(C), and composite video baseband(Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Veriflog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 42K gates and is implemented by using 0.6um CMOS process.

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Performance Simulation of a Turboprop Engine for Basic Trainer

  • Kong, Changduk;Ki, Jayoung;Chung, Sukchoo
    • Journal of Mechanical Science and Technology
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    • v.16 no.6
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    • pp.839-850
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    • 2002
  • A performance simulation program for the turboprop engine (PT6A-62), which is the power plant of the first Korean indigenous basic trainer KT-1, was developed for performance prediction, development of an EHMS (Engine Health Monitoring System) and the flight simulator. Characteristics of components including compressors, turbines, power turbines and the constant speed propeller were required for the steady state and transient performance analysis with on and off design point analysis. In most cases, these were substituted for what scaled from similar engine components'characteristics with the scaling law. The developed program was evaluated with the performance data provided by the engine manufacturer and with analysis results of GASTURB program, which is well known for the performance simulation of gas turbines. Performance parameters such as mass flow rate, compressor pressure ratio, fuel flow rate, specific fuel consumption and turbine inlet temperature were discussed to evaluate validity of the developed program at various cases. The first case was the sea level static standard condition and other cases were considered with various altitudes, flight velocities and part loads with the range between idle and 105% rotational speed of the gas generator. In the transient analysis, the Continuity of Mass Flow Method was utilized under the condition that mass stored between components is ignored and the flow compatibility is satisfied, and the Modified Euler Method was used for integration of the surplus torque. The transient performance analysis for various fuel schedules was performed. When the fuel step increase was considered, the overshoot of the turbine inlet temperature occurred. However, in case of ramp increase of the fuel longer than step increase of the fuel, the overshoot of the turbine inlet temperature was effectively reduced.

Data Decision Aided Timing Tracker in IR-UWB System using PPM (PPM 변조방식의 IR-UWB 시스템에서 데이터 결정방식을 이용한 타이밍 추적기)

  • Ko, Seok-Jun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.1
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    • pp.98-105
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    • 2007
  • In this paper, we propose a timing detector using suboptimal maximum likelihood method. The proposed method has an simple reference signal generator. Additionally, timing detector's gain of the proposed method is the same to Early-Late gate and ML method. We reveal that tracking range of time tracker is narrow because of using data-decision, that is, tracking range is ${\pm}0.06ns$ for the 4-order Gaussian monocycle with 0.7ns pulse width. Therefore we can find that searcher must have very accurate acquisition procedure. When estimating a performance of time tracker, we consider a jitter in transmitter and receiver's pulse generation process as well as background noise. By using computer simulation, we propose mean/variance of timing detector and tracking process. Also we consider a mobility in tracking process, i.e., timing error modeled ramp function. In order to propose a performance of time tracker, we consider only one correlation demodulator.

Design of Single-Inductor Dual-Output Boost-Boost DC-DC Converter with Dual Feedback Loop Based on Relative Sawtooth Generator (Dead-time을 갖는 톱니파 발생기를 이용한 이중 피드백 루프 기반 단일 인덕터 이중 출력 승압형 변압기 설계)

  • Yun, Dam;Kim, Dong-Young;Lee, Kang-Yoon
    • Journal of IKEEE
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    • v.18 no.2
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    • pp.220-227
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    • 2014
  • This paper presents a control method of Single-Inductor Dual-Output DC-DC Converter using Common mode feedback and differential feedback loops. To generate duty used for differential mode feedback loop, this paper propose relative sawtooth circuit using current divider circuit which makes ramp signal with variable dead-time. Two outputs of the Single-Inductor Dual-Output DC-DC Converter are specified for 2.8 V and 4.2 V with input voltage 2.5 V. The maximum conversion efficiency of designed SIDO DC-DC Converter is 95% at total output power of 539mW. Cross regulations of Boost1 and Boost2 are 3.57% and 4% each, when increasing twice times output current.

Design of a CCM/DCM dual mode DC-DC Buck Converter with Capacitor Multiplier (커패시터 멀티플라이어를 갖는 CCM/DCM 이중모드 DC-DC 벅 컨버터의 설계)

  • Choi, Jin-Woong;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.9
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    • pp.21-26
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    • 2016
  • This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.