• Proceedings of the Korea Information Processing Society Conference
• /
• 2015.04a
• /
• pp.526-529
• /
• 2015

이 연구에서는 노드 & 컴포넌트 기반 개발(Node & Component Based Development, NCBD)을 지원하는 게임엔진을 직접 설계, 제작하는 내용이다. NCBD를 지원하는 게임엔진은 이미 상용화된 유명게임엔진들(Unity, Unreal, Cocos2d-x)이 공통으로 지원하는 프로그래밍 패러다임이며, 이러한 노드 & 캠포넌트 구조는 깊은 상속구조를 지향하는 구조보다 유연하고 직관적이다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2008.11a
• /
• pp.75-77
• /
• 2008

Nowadays, as the indices of the major search engines grow to a tremendous proportion, vertical search services can help customers to find what they need. Search Engine is one of the reasons for Internet shopping success in today's world. The import one part of search engine is clustering data. The objective of this paper is to explore a k-means++ algorithm to calculate the clustering data which in the Internet shopping environment. The experiment results shows that the k-means++ algorithm is a faster algorithm to achieved a good clustering.

• Journal of KIISE:Databases
• /
• v.37 no.6
• /
• pp.300-307
• /
• 2010

According to growth of web, data processing technology is developing. In the Web of next generation, high-speed or high-volume data processing technologies for various wire-wireless users, USN and RFID are developing too. In this paper, we propose a high-volume data processing technology using Complex Event Processing(CEP) engine. CEP is the technology to process complex events. CEP Engine is the following characteristics. First it collects a high-volume event(data). Secondly it analyses events. Finally it lets event connect to new actions. In other words, CEP engine collects, analyses, filters high-volume events. Also it extracts events using pattern-matching for registered events and new events. As the results extracted. We use it by an input event of other work, real-time response for demanded event and can trigger to database for only valid data.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.533-536
• /
• 2000

In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

• Journal of Broadcast Engineering
• /
• v.18 no.4
• /
• pp.535-542
• /
• 2013

In this paper, we proposed a advanced hardware engine architecture for high speed and high detection rate image recognitions. We adopted the HOG-LBP feature extraction algorithm and more parallelized architecture in order to achieve higher detection rate and high throughput. As a simulation result, the designed engine which can search about 90 frames per second detects 97.7% of pedestrians when false positive per window is $10^{-4}$.

• The KIPS Transactions:PartA
• /
• v.10A no.2
• /
• pp.111-122
• /
• 2003

Military wargame simulation models must support the HLA in order to facilitate interoperability with other simulations, and using parallel simulation engines offer efficiency in reducing system overhead generated by propelling interoperability. However, legacy military simulation model engines process events using sequential event-driven method. This is due to problems generated by parallel processing such as synchronous reference to global data domains. Additionally. using legacy simulation platforms result in insufficient utilization of multiple CPUs even if a multiple CPU system is under use. Therefore, in this paper, we propose conversing the simulation engine to an object model-based parallel simulation engine to ensure military wargame model's improved system processing capability, synchronous reference to global data domains, external simulation time processing, and the sequence of parallel-processed events during a crash recovery. The converted parallel simulation engine is designed and implemented to enable parallel execution on a multiple CPU system (SMP).

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2012.04a
• /
• pp.208-209
• /
• 2012

This paper describes a comprehensive process and range of design tools and components for providing Improved perception of engine sound for mass production vehicles by the generation of finely tuned engine harmonics.

• Journal of Digital Contents Society
• /
• v.8 no.4
• /
• pp.615-622
• /
• 2007

A game engine should have the architecture that can manage various interactions between entities in a game for offering users various game experience. For this purpose, the game engine architecture based on message system is used. But only by this message based system, it is difficult to change game world continuously according to some storylines. The reason of this is event-driven system like message based system is appropriate for processing individual message but is not appropriate for processing more bigger logical work unit. For this purpose this paper proposes the storyline entity. The storyline entity has logical flows for a storyline and is called by engine continuously. By this proposed game engine architecture he or she can maintain free game experience by message based system and can add some progressing of storylines.

• IE interfaces
• /
• v.14 no.3
• /
• pp.263-271
• /
• 2001

MPLS LER is located at the boundary of MPLS domain as an ingress or an egress router and plays a role in connecting with the existing Internet. Among the components of the MPLS LER, forwarding engine(FE) is a key device which assigns a label to an IP packet by analyzing the destination address of its header in order to enter the MPLS domain, or restructures the cells from MPLS domain into IP packet by reversely processing. In this paper, we investigate the design of FE by analyzing the traffic performance of its components and estimate the IP packet processing capacity of a FE using queueing model and simulation. It is found that the maximum IP packet processing capacity of the Forwarding Engine is about 150,000 packets/sec.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.5B
• /
• pp.465-475
• /
• 2004

Transport Control Protocol (TCP) has been implemented in software running on CPU in end systems, and the protocol processing has appeared as a new bottleneck due to advanced link technology. TCP processing is a critical issue in Storage Area Network (SAN) such as iSCSL, and the overall performance of the Storage Area Network heavily depends on speed of TCP processing. TCP Engine implemented in hardware reduces the load of CPU in end systems as well as accelerates the protocol processing, and hence high speed data processing is achieved. In this paper, we have proposed a hardware engine for TCP processing. TCP engine consists of three major block, TCP Connection block Rx TCP block and Tx TCP block TCP Connection block is responsible for managing TCP connection states. Rx TCP block is responsible for receive flow which receives packets from network and sends to CPU. Rx TCP performs header and data processing and sends header information to TCP connection block and Tx TCP block It also assembles out-of-ordered data to in-ordered before it transfers data to CPU. Tx TCP block is responsible for transmit flow which transfers data from CPU to network. Tx TCP performs retransmission for reliable data transfer and management of transmit window and sequence number. Various test-cases are used to verify the TCP functions. The TCP Engine is synthesized using 0.18 micron technology and results in 51K gates not including buffers for temporal data storage.