• Journal of Information Processing Systems
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• v.1 no.1 s.1
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• pp.27-31
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• 2005

Vehicle detector system based on image processing technology is a significant domain of ITS (Intelligent Transportation System) applications due to its advantages such as low installation cost and it does not obstruct traffic during the installation of vehicle detection systems on the road[1]. In this paper, we propose architecture for vehicle detection by using image processing. The architecture consists of two main parts such as an image processing part, using high speed FPGA, decision and calculation part using CPU. The CPU part takes care of total system control and synthetic decision of vehicle detection. The FPGA part assumes charge of input and output image using video encoder and decoder, image classification and image memory control.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.90-97
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• 2006

In this paper, we present a cost-effective architecture of high-speed soft-decision Viterbi decoder for Multi-band OFDM(MB-OFDM) systems. In the design of modem for MB-OFDM systems, a parallel processing architecture is general]y used for the reliable hardware implementation, because the systems should support a very high-speed data rate of at most 480Mbps. A Viterbi decoder also should be designed by using a parallel processing structure and support a very high-speed data rate. Therefore, we present a optimized hardware architecture for 4-way parallel processing Viterbi decoder in this paper. In order to optimize the hardware of Viterbi decoder, we compare and analyze various ACS architectures and find the optimal one among them with respect to hardware complexity and operating frequency The Viterbi decoder with a optimal hardware architecture is designed and verified by using Verilog HDL, and synthesized into gate-level circuits with TSMC 0.13um library. In the synthesis results, we find that the Viterbi decoder contains about 280K gates and works properly at the speed required in MB-OFDM systems.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10b
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• pp.993-996
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• 2001

본 논문에서는 정책기반 네트워크보안 프레임워크의 전체적인 구조와 주요 아키텍쳐에 대해서 논하고 특히 보안정책 서버의 역할을 담당하는 네트워크보안제어서버의 구조와 메커니즘에 대해 구체적으로 기술한다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.381-382
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• 2006

In this paper, we present an efficient architecture for connected speech recognition that can be efficiently implemented with FPGA. The architecture consists of newly derived two-level dynamic programming (TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the computational speed from avoiding propagation delays in multiplications. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.123-124
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• 2024

최근 차량 내 소프트웨어가 급속도로 발전하면서, 새로운 차량 아키텍처인 Zonal Architecture 에 대한 관심이 높아지고 있다. 따라서 본 연구에서는 Zonal Architecture 을 실제 유아용 전동차에 적용해 보고, Zonal Architecture 의 달성 조건 중 하나인 센서간 시간 동기화를 구현한다.

• Journal of Satellite, Information and Communications
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• v.9 no.1
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• pp.65-69
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• 2014

The Communication, Ocean and Meteorological Satellite(COMS) data processing system(CMDPS) has developed to support the meteorological observation and weather prediction by NMSC(National Meteorological Satellite Center) and it is generating the 16 kind of meteorological data(Level 2 product). Unfortunately, currently CMDPS has some problems in terms of the system maintenance and the integrated software efficiency, and the extension to support the next generation meteorological satellite data processing. To solve this problems, in this paper, we suggest the extensible component-based system architecture for COMS meteorological data processing with consideration of identified issues. Proposed system is adapted the component-based frameworks with extensible architecture. We expects that this system will be provide easy ways to develop new satellite data processing algorithms and to maintain the system.

• Journal of KIISE
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• v.42 no.3
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• pp.399-407
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• 2015

Wireless sensor networks are used for data collection and processing from the surrounding environment for various applications. Since wireless sensor nodes operate on low computing power, restrictive battery capacity, and low network bandwidth, their architecture model has greatly affected the performance of applications. If applications have high computation complexity or require the real-time processing, the centralized architecture in wireless sensor networks have a delay in data processing. Otherwise, if applications only performed simple data collection for long period, the distributed architecture wasted battery energy in wireless sensors. In this paper, the energy consumption and processing delay were analyzed in centralized and distributed sensor networks. In addition, we proposed a new hybrid architecture for wireless sensor networks. According to the characteristic of applications, the proposed method had the optimal number of wireless sensors in wireless sensor networks.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.32-39
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• 2015

The voice communications with wireless backbone based networks are evolving into a packet switching VoIP systems. In those networks, a call processing scheme is required for management of subscribers and connection between them. A VoIP service scheme for those systems requires reliable subscriber management and connection establishment schemes, but the conventional call processing schemes based on the centralized server has lack of reliability. Thus, the mutual-backup architecture of SIP-servers is required to ensure efficient subscriber management and reliable VoIP call processing capability, and the synchronization and call processing schemes should be changed as the architecture is changed. In this paper, a mutual-backup architecture of SIP-servers is proposed for wireless backbone based networks. A message format for synchronization and information exchange between SIP servers is also proposed in the paper. This paper also proposes a FSM scheme for the fast call processing in unreliable networks to detect multiple servers at a time. The performance analysis results show that the mutual backup server architecture increases the call processing success rates than conventional centralized server architecture. Also, the FSM scheme provides the smaller call processing times than conventional SIP, and the time is not increased although the number of SIP servers in the networks is increased.

• Journal of Korean Institute of Industrial Engineers
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• v.39 no.1
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• pp.1-9
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• 2013

The current manufacturers have generated tremendous amount of digitized product data to efficiently share and exchange it with other stakeholders or various software systems for product development. The digitized product data is a valuable asset for manufacturers, and has a potential to support high level strategic decision makings needed at many stages in product development. However, the lack of studies on extraction of key performance indicators(KPIs) from product data management(PDM) databases has prohibited manufacturers to use the product data to support the decision makings. Therefore this paper examines a possibility of an architecture that supports KPIs for evaluation of product development performances, by applying multidimensional product data model and on-line analytic processing(OLAP) to operational databases of product data management. To validate the architecture, the paper provides a prototype product data management system and OLAP applications that implement the multidimensional product data model and analytic processing.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.