• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.41 no.4
• /
• pp.1-8
• /
• 2004

When the PCI 2.2 bus master requests data using Memory Read command, the target device my hold PCI bus without data transfer for a long time because the target device requires time to prefetch data internally. Because the PCI bus usage efficiency and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the performance. But the mechanism doesn't fully improve performance because the target device doesn't blow prefetch data size exactly. In this paper, we propose a new method to transfer data efficiently when the bus master reads data from the target device. The bus master informs the target device the exact read data size using prefetch request using Memory Write command. The simulation result shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about 10%.

• Journal of KIISE:Computer Systems and Theory
• /
• v.35 no.1
• /
• pp.30-43
• /
• 2008

Memory reference instructions such as loads or stores are critical factors that limit the processing power of processor. The prefetching technique is an effective way to reduce the latency caused from memory access. However, excessively aggressive prefetch leads to cache pollution so as to cancel out the advantage of prefetch. In this study, four filtering schemes have been compared and evaluated which dynamically decide whether to begin prefetch after referring a filtering table to decrease cache pollution. First, A bi-states scheme has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete state scheme has been introduced to be used as a reference for the comparative study. A block address lookup scheme has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the bi-states scheme, the contents of each entry have the fields the same as the complete state scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. Experimental results from commonly used general benchmarks and multimedia programs show that average cache miss ratio have been decreased by 10.5% for the block address lookup scheme(BAL) compare to conventional dynamic filter scheme(2-bitSC).

• The KIPS Transactions:PartD
• /
• v.13D no.4 s.107
• /
• pp.463-476
• /
• 2006

R-trees have been traditionally optimized for the I/O performance with the disk page as the tree node. Recently, researchers have proposed cache-conscious variations of R-trees optimized for the CPU cache performance in main memory environments, where the node size is several cache lines wide and more entries are packed in a node by compressing MBR keys. However, because there is a big difference between the node sizes of two types of R-trees, disk-optimized R-trees show poor cache performance while cache-optimized R-trees exhibit poor disk performance. In this paper, we propose a cache and disk optimized R-tree, called the PR-tree (Prefetching R-tree). For the cache performance, the node size of the PR-tree is wider than a cache line, and the prefetch instruction is used to reduce the number of cache misses. For the I/O performance, the nodes of the PR-tree are fitted into one disk page. We represent the detailed analysis of cache misses for range queries, and enumerate all the reasonable in-page leaf and nonleaf node sizes, and heights of in-page trees to figure out tree parameters for best cache and I/O performance. The PR-tree that we propose achieves better cache performance than the disk-optimized R-tree: a factor of 3.5-15.1 improvement for one-by-one insertions, 6.5-15.1 improvement for deletions, 1.3-1.9 improvement for range queries, and 2.7-9.7 improvement for k-nearest neighbor queries. All experimental results do not show notable declines of the I/O performance.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.423-426
• /
• 2004

본 논문에서는 저 전력 마이크로프로세서를 개발하기 위해 ARM7 마이크로프로세서와 명령어 호환을 갖는 32비트 RISC 구조의 마이크로프로세서를 설계하였다. 저 전력 ARM7 마이크로프로세서 IP 구현을 위하여 새로운 정수 나눗셈 명령어를 정의하고 이를 적용하는 회로를 설계하여 제수가 피제수보다 큰 경우 6.4nW, 그 이외의 경우에는 76.5 nW를 소모하여 기존의 방법보다 $140{\~}860\%$ 까지 개선되었음을 측정하였다. 또한 Multi-cycle 명령어 발생시 Prefetch에 의한 전력 소모를 줄이기 위하여 명령어의 condition code를 미리 결정함으로써 $50\%$의 prefetch 동작 횟수를 줄였다. 그 결과 저 전력 파이프라인의 경우에는 1.943mW/1MHz의 소비 전력이 측정되었다.

• Journal of the Korea Computer Industry Society
• /
• v.5 no.4
• /
• pp.453-460
• /
• 2004

SPAM mails become a serious social problem all of the world and the products for SPAM prevention are coming to the market. This study classifies the existing SPAM prevention solutions according to the patterns to be set up and the judging SPAM methods, and analyses the merits and demerits of them. This study also draws problems of the existing SPAM Prevention solutions and suggests a new URL Prefetch method, a new filtering method which have been out of use. And it draws synergistic effects of SPAM prevention by this new method and suggests SPAM Prevention solution by HTML Pattern method

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.11B
• /
• pp.1939-1947
• /
• 2000

본 논문에서는 명령어의 효율적인 페치를 위해 분기 타겟 주소 전체를 사용하지 않고 캐쉬 메모리(cache memory) 내의 적은 비트 수로 인덱싱 하여 한 클럭 사이클 안에 최대 4개의 명령어를 다음 파이프라인으로 보내줄 수 있는 방법을 제시한다. 본 프리페치 유닛은 크게 나누어 3개의 영역으로 나눌 수 있는데, 분기에 관련하여 미리 부분적으로 명령어를 디코드 하는 프리디코드(predecode) 블록, 타겟 주소(NTA : Next Target Address) 테이블 영역을 추가시킨 명령어 캐쉬(instruction cache) 블록, 전체 유닛을 제어하고 가상 주소를 관리하는 프리페치(prefetch) 블록으로 나누어진다. 사용된 명령어들은 SPARC(Scalable Processor ARChitecture) V9에 기준 하였고 구현은 Verilog-HDL(Hardwave Description Language)을 사용하여 기능 수준으로 기술되고 검증되었다. 구현된 프리페치 유닛은 명령어 흐름에 분기가 존재하더라도 단일 사이클 안에 4개까지의 명령어들을 정확한 예측 하에 다음 파이프라인으로 보내줄 수 있다. 또한 NTA를 사용한 방법은 같은 수의 레지스터 비트를 사용하였을 때 BTB(Branch Target Buffer)를 사용하는 방법과 비교하여 2배정도 많은 개수의 분기 명령 주소를 저장할 수 있는 장점이 있다.

• Journal of the Korean Data and Information Science Society
• /
• v.21 no.3
• /
• pp.605-619
• /
• 2010

Caching of frequently accessed data in multi-hop ad hoc environment is a technique that can improve data access performance and availability. Cooperative caching, which allows sharing and coordination of cached data among several clients, can further en-hance the potential of caching techniques. In this paper, we propose a fuzzy cooperative caching scheme in mobile ad hoc networks. The cache management of the proposed caching scheme not only uses adaptively CacheData or CachePath based on data sim-ilarity and data utility, but also uses the replacement manager based on data pro t. Also, the proposed caching scheme uses a prefetch manager. When the TTL of the cached data expires, the prefetch manager evaluates the popularity index of the data. If the popularity index is larger than a threshold, the data is prefetched. Otherwise, its space is released. The performance of the proposed scheme is evaluated analytically and is compared to that of other cooperative caching schemes.

• Journal of IKEEE
• /
• v.14 no.2
• /
• pp.69-75
• /
• 2010

A 3D graphics pipeline is largely divided into geometry stage and rendering stage. In this paper, we propose a method that accelerates a geometry processing in multi-core GP-GPU, using dual-phase structure. It can be improved by parallel data processing using SIMD of GP-GPU, dual-phase structure and memory prefetch. The proposed architecture improves approximately 19% of performance when it use all the features.

• Proceedings of the Korean Information Science Society Conference
• /
• 2007.06b
• /
• pp.441-444
• /
• 2007

본 논문에서는 객체기반 IP 스토리지를 이용하여 모바일 기기에서 멀티미디어 콘텐츠 재생에 적합한 저전력 객체기반 모바일 스토리지 시스템 구조를 제안한다. 멀티미디어 콘텐츠의 재생 성능을 높이기 위해 모바일 단말 측 OSD 계층에 버퍼 캐시(buffer cache)와 선반입(prefetch) 기능을 추가한다. 그리고 모바일 단말의 WLAN 전력제어를 통하여 WLAN이 가능한 한 오랜 시간 동안 Sleep 상태 또는 Power Off 상태에 있을 수 있도록 하여 전력의 소비를 줄인다. 본 연구에서는 캐시 및 선반입 기능을 위해 버퍼 캐시관리자(buffer cache manager)와 선반입 관리자(prefetch manager)를 설계하였고, WLAN 전력관리 기능을 위해 WLAN 관리자(WLAN manager)를 설계하였다.

• Journal of Korea Multimedia Society
• /
• v.3 no.2
• /
• pp.101-111
• /
• 2000

Resource managing is very difficult because the multimedia data compressed by a VBR shows a bit rate change within high range, Therefore, the VOD server should use the prefetch method in order to improve system utilization, such as prefetching data in the overload period by a meta table that is the reference pattern of MPEG data which is analyzed off line. This prefetch method will not result in a failure to display at overload, however, this method can not keep a minimum loading time and low costs, because the prefetched section is being maximizes. In this paper, we suggest another method that the system utilization can be improved using the fixed prefetched section to keep loading time and costs under a constant range at overload. But this technique will result in a failure to display, due to fixed prefetched section. Rut, in this paper we suggest a drop module that drops only the B frame in the GOP, consistently distributes a lower drop in media quality for the user.