• Journal of IKEEE
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• v.19 no.3
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• pp.455-459
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• 2015

This paper proposes a dispatch unit of GP-GPU with SIMT architecture to support the acceleration of general-purpose operation as well as graphics processing. If all the information of an operand used instructions issued from the warp scheduler is decoded, an unnecessary operand load occurs, resulting in register loads. To resolve this problem, this paper proposes a method that can reduce the operand load and the load on the resister by decoding only the information of the operand using a pre-decoding method. The operand information from the dispatch unit is passed to the operand selection unit with preventing register bank collisions. Thus the overall performance are improved. In the simulation test, the total clock cycles required by processing 10,000 arbitrary instructions issued from the wrap scheduler using ModelSim SE 10.0b are measured. It shows that the application of the dispatch unit equipped with the pre-decoding function proposed in this paper can make an improvement of about 12% in processing performance compared to the conventional method.

• Journal of IKEEE
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• v.22 no.4
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• pp.1168-1174
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• 2018

For the initial state of NAND flash memories, error-free and single-error cases are dominant due to a good channel environment on memory cells. It is important to deal with such cases, which affects the overall system performance. However, the conventional schemes for polar codes equally decode the codes even for the error-free and single-error cases since they cannot classify and decode separately. In this paper, a new pre-processing scheme for polar codes is proposed so as to improve the overall decoding latency by decoding the frequent error-free and single-error cases. Before the ordinary decoding process, the proposed scheme first decodes the frequent error-free and single-error cases. According to the experimental results, the proposed pre-processing scheme decreases the average decoding latency by 64% compared to the conventional scheme for (1024, 512) polar codes.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.280-280
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• 2004

• Journal of Communications and Networks
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• v.17 no.3
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• pp.213-220
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• 2015

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9A
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• pp.679-684
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• 2009

A collision dispersion scheme based on orthogonal pre-spreading is proposed to reduce the effect of collisions that occur in orthogonal code hopping multiplexing(OCHM). The OCHM scheme was previously proposed to accommodate a significantly larger number of low-activity bursty channels than the number of orthogonal codewords. The proposed scheme greatly reduces the required SNR in channel decoding. In addition, the proposed scheme can be applied to OFHM based on OFDM.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.12
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• pp.28-33
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• 2007

We present a space-time trellis coded OFDM system in flow fading channels. Generalized principal ratio combining (GPRC) is also analyzed theoretically in frequency domain. The analysis show that the decoding metric of GPRC include the metrics of maximum likelihood (ML) and PRC. The computer simulations with M-PSK modulation are obtained in frequency flat and frequency selective lading channels. The decoding complexity and simulation running times are also evaluated among the decoding schemes.

• Korean Journal of Child Studies
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• v.22 no.1
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• pp.163-175
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• 2001

This study investigated the effect on children's literacy of teacher-child discussion about the contents of storybooks. The subjects were 10 experimental and 10 control 5-year-old kindergarten children in Cheongju. The experimental design was the Split Plot design. The research instruments used for pre- and post-tests were the Vocabulary Decoding Competence Test(Lee, 1998), Writing Competence Test(Lee & Lee, 1990), Story Comprehension Competence Test(Lee, 1998; Morrow, 1990), and the Emergent Reading Ability Judgements for Favorite Storybooks(Sulzby, 1985). Data were analyzed by ANOVA with repeated measures. Results showed that the teacher-child discussions about the contents of storybooks were effective for improving children's competence in decoding vocabulary, writing, and story comprehension but not for improving emergent reading ability.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.285-288
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• 1998

Viterbi docoder is a maximum likelihood decoding method for convolution coding used in satellite and mobile communications. In this paper, a Viterbi decoder with constraint length of K=7, 3-soft decision and traceback depth of $\Gamma$=96 for convolution code is implemented using VHDL. The hardware size of designed decoder is reduced by 4 bit pre-traceback in the survivor memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.550-556
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• 2016

Polar codes are one of the most favorable capacity-achieving codes due to their simple structure and low decoding complexity. However, because of the disappointing decoding performance realized using conventional successive cancellation (SC) decoders, polar codes cannot be used directly in practical applications. In contrast to conventional SC decoders, list SC (SCL) decoders with large list sizes (e.g. 32) achieve performances very close to those of maximum-likelihood (ML) decoders. In SCL decoders with large list sizes, however, hardware increase is a severe problem because an SCL decoder with list size L consists of L copies of an SC decoder. In this paper, we present a low-area SCL decoder architecture that applies the proposed merged processing element-sharing (MPES) algorithm. A merged processing element (MPE) is the basic processing unit in SC decoders, and the required number of MPEs is L(N-1) in conventional SCL decoders. Using the proposed algorithm reduces the number of MPEs by about 70% compared with conventional SCL decoders when the list size is larger than 32.

• Journal of Communications and Networks
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• v.16 no.5
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• pp.479-484
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• 2014

In this paper, we consider the construction of cyclic and quasi-cyclic structured q-ary low-density parity-check (LDPC) codes over a designated small field. The construction is performed with a pre-defined sliding-window, which actually executes the regular mapping from original field to the targeted field under certain parameters. Compared to the original codes, the new constructed codes can provide better flexibility in choice of code rate, code length and size of field. The constructed codes over small fields with code length from tenths to hundreds perform well with q-ary sum-product decoding algorithm (QSPA) over the additive white Gaussian noise channel and are comparable to the improved spherepacking bound. These codes may found applications in wireless sensor networks (WSN), where the delay and energy are extremely constrained.