• 한국전자파학회논문지
• /
• 제23권11호
• /
• pp.1248-1255
• /
• 2012

본 논문에서는 DVB-S2에 제시된 LDPC 복P호기에 대하여 효율적인 알고리즘을 제안하고 고속화 하여, 이에 따른 FPGA구현 결과를 제시하였다. 고속 LDPC 복호기를 구현하기 위해서는 알고리즘 측면과 구현 측면에서 여러 가지 문제점이 있다. 알고리즘 측면에서는 첫째, LDPC 부호화 방식은 큰 블록 사이즈 및 많은 반복 횟수를 요구하므로 복호 속도를 높이기 위해서는 동일한 성능을 유지하면서 반복 횟수를 줄일 수 있는 알고리즘이 필요하다. 본 논문에서는 이를 위해 체크 노드를 기반으로 하여 복호화 과정을 거치는 horizontal shuffle scheduling(HSS) 알고리즘을 적용하여 기존의 반복 횟수를 줄일 수 있는 방안을 연구 하였다. 구현 측면에서 복호 속도를 높이기 위해서는 데이터의 많은 병렬 처리가 필요하다. 이러한 병렬 처리에 의해 노드 업데이트 연산 역시 병렬 처리가 가능하다. Check Node Update의 경우 look up table(LUT)이 필요하다. 이는 critical path의 주요 원인이 되는 부분으로 LUT 연산을 하지 않고 성능 열화를 최소화 하는 self-correction normalized min sum(SC-NMS) 연산 방식을 제안하였고, 최적의CNU 연산 방식에 따른 복호기 구조를 제안하고 FPGA 구현 결과, 복호 속도가 약 40 % 개선됨을 알 수 있다.

• 대한전기학회논문지
• /
• 제34권10호
• /
• pp.389-398
• /
• 1985

Recently maximum power demand of our country has become to be under the great in fluence of electric cooling and air conditioning demand which are sensitive to weather conditions. This paper presents the technique and algorithm to forecast the long-term maximum power demand considering the characteristics of electric power and weather variable. By introducing a weather load model for forecasting long-term maximum power demand with the recent statistic data of power demand, annual maximum power demand is separated into two parts such as the base load component, affected little by weather, and the weather sensitive load component by means of multi-regression analysis method. And we derive the growth trend regression equations of above two components and their individual coefficients, the maximum power demand of each forecasting year can be forecasted with the sum of above two components. In this case we use the coincident dry bulb temperature as the weather variable at the occurence of one-day maximum power demand. As the growth trend regression equation we choose an exponential trend curve for the base load component, and real quadratic curve for the weather sensitive load component. The validity of the forecasting technique and algorithm proposed in this paper is proved by the case study for the present Korean power system.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2016년도 전력전자학술대회 논문집
• /
• pp.359-360
• /
• 2016

This paper presents a new predictive current control (PCC) method to achieve the coordinate control of power and current of the matrix converter under unbalanced input voltages. In order to control the power fluctuation in the input side, the flexible source current reference is generated based on the positive-negative sequence components of the input voltage. The optimal switching state to adjust source and load currents is selected by minimization the cost function which is obtained from the sum of the absolute errors between the current references and their predictive values. Simulation results are given to validate the effectiveness of the proposed PCC method.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 하계학술대회 논문집 C
• /
• pp.1419-1421
• /
• 1999

CADPAD program has been used as a distribution planning tool in KEPCO since 1989. In recent we've been upgraded the I/O modules. Now we analyze the key algorithm of FEEDERSITE module. The objective function is represented by the sum of the multiples of Power flow and cost. To minimize the objective function, it is used to Linear Programming algorithm. We will show this algorithm in this paper.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
• /
• pp.191-194
• /
• 2001

In this paper, we propose a series active power filter control method to compensate current harmonics and unbalanced source voltage. The system is composed of series active power filter and shunt passive filer that are tuned 5th and 7th harmonics. In this conventional system, series active power filter complements drawbacks of the shunt passive filter, namely improves harmonic compensation characteristics, and compensates unbalanced source voltage. In the proposed algorithm, compensation voltage for harmonic reduction is calculated by performance function, and compensation voltage for unbalanced source voltage is calculated in based on a synchronous reference frame. So, ultimate compensation voltage is sum of those two compensation voltages. By computer simulation, we verify the excellency of proposed method.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.371-372
• /
• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
• /
• pp.2199-2201
• /
• 2005

High voltage power supply with pulse load($4.5{\mu}s$ and PRF 60Hz) condition is investigated which is of interest for applications like Klystron modulator power supplies with output voltage of 50kV. The performance specifications with this type of power supplies are very stringent demanding tight regulation(<0.01%) and high efficiency(> 85%). The solution to this problem as a single stage converter is very difficult. The final output voltage is obtained as sum of the output of SCPS & PCPS. The combination of the two stages can satisfy the pulse load specifications. The analysis of the voltage and power division between SCPS & PCPS has been done for the proposed topology. It has studied under various operating conditions of line and load. Simulation results are validated by experimental results.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제12권11호
• /
• pp.5382-5403
• /
• 2018

In this paper, for a spectrum sensing purpose, we heuristically established a test statistic (TS) from a sample covariance matrix (SCM) for multiple antennas based cognitive radio. The TS is formulated as a scaled-energy which is calculated as a sum of scaled diagonal entries of a SCM; each of the diagonal entries of a SCM scaled by corresponding row's Euclidean norm. On the top of that, by combining theoretical results together with simulation observations, we have approximated a decision threshold of the TS which does not need prior knowledge of noise power and primary user signal. Furthermore, simulation results - which are obtained in a fading environment and in a spatially correlating channel model - show that the proposed method stands effect of noise power mismatch (non-uniform noise power) and has significant performance improvement compared with state-of-the-art test statistics.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제17권1호
• /
• pp.202-215
• /
• 2023

This paper proposes a non-orthogonal multiple access (NOMA) based low-complexity relaying approach for multiuser cellular two-way relay channels (CTWRCs). In the proposed scheme, the relay detects the signal using successive interference cancellation (SIC) and re-generates the transmit signal with zero-forcing (ZF) transmit precoding. The achievable data rates of the NOMA-based multiuser two-way relaying (TWR) approach is analyzed. We further study the power allocation among different data streams to maximize the weighted sum-rate (WSR). We re-form the resultant non-convex problem into a standard monotonic program. Then, we design a polyblock outer approximation algorithm to sovle the WSR problem.The proposed optimal power allocation algorithm converges fast and it is shown that the NOMA-TWR-OPA scheme outperforms a NOMA benchmark scheme and conventional TWR schemes.

• 대한전자공학회논문지TC
• /
• 제42권7호
• /
• pp.35-40
• /
• 2005

본 논문에서는 900MHz 대역 중저속 무선 통신용 칩에 이용되는 3차 ${\Delta}{\sum}$ modulator를 사용한 Fractional-N PLL 주파수 합성기를 설계 및 제작하였다 우수한 위상노이즈 특성을 얻기 위해 노이즈 특성이 좋은LC VCO를 사용하였다. 그리고 고착시간을 줄이기 위해서 Charge Pump의 펌핑 전류를 주파수 천이 값에 따라 조절할 수 있도록 제작하였고 PFD의 참조 주파수를 3MHz까지 높였다. 또한 참조 주파수를 높이는 동시에 PLL의 최소 주파수 천이 간격을 10KHz까지 줄일 수 있도록 하기위하여 36/37 Fractional-N 분주기를 제작하였다. Fractional Spur를 줄이기 위해서 3차 ${\Delta}{\sum}$ modulator를 사용하였다. 그리고 VCO, Divider by 8 Prescaler, PFD, 및 Charge Pump는 0.25um CMOS공정으로 제작되었으며, 루프 필터는 외부 컴포넌트를 이용한 3차RC 필터로 제작되었다. 그리고 Fractional-N 분주기와 3차 ${\Delta}{\sum}$ modulator는 VHDL 코드로 작성되었으며 Xilinx Spartan2E을 사용한 FPGA 보드로 구현되었다. 측정결과 PLL의 출력 전력은 약 -11dBm이고, 위상노이즈는 100kHz offset 주파수에서 -77.75dBc/Hz이다. 최소 주파수 간격은 10kHz이고, 최대 주파수 천이는 10MHz이고, 최대 주파수 변이 조건에서 고착시간은 약 800us이다.