• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5357-5381
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• 2018

Cloud computing offers a wide range of on-demand resources over the internet. Utility-based resource allocation in cloud data centers significantly increases the number of cloud users. Heavy usage of cloud data center encounters many problems such as sacrificing system performance, increasing operational cost and high-energy consumption. Therefore, the result of the system damages the environment extremely due to heavy carbon (CO2) emission. However, dynamic allocation of energy-efficient resources in cloud data centers overcomes these problems. In this paper, we have proposed Energy and Service Level Agreement (SLA) Aware Resource Allocation Heuristic Algorithms. These algorithms are essential for reducing power consumption and SLA violation without diminishing the performance and Quality-of-Service (QoS) in cloud data centers. Our proposed model is organized as follows: a) SLA violation detection model is used to prevent Virtual Machines (VMs) from overloaded and underloaded host usage; b) for reducing power consumption of VMs, we have introduced Enhanced minPower and maxUtilization (EMPMU) VM migration policy; and c) efficient utilization of cloud resources and VM placement are achieved using SLA-aware Modified Best Fit Decreasing (MBFD) algorithm. We have validated our test results using CloudSim toolkit 3.0.3. Finally, experimental results have shown better resource utilization, reduced energy consumption and SLA violation in heterogeneous dynamic cloud environment.

• ETRI Journal
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• v.36 no.4
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• pp.635-642
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• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.22-28
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• 2009

As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.641-650
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• 2008

As portable devices are used widely, power management algorithm is essential to extend battery use time on small-sized battery power. Although many methods have been proposed, they assumed the voltage transition overhead was negligible or was considered partially. However, the voltage transition overhead might not guarantee to schedule real-time tasks in portable multimedia systems. This paper proposes the adaptive power-aware algorithm to minimize the power consumption by considering the voltage transition overhead. It selects only a few discrete frequencies from the whole frequencies of a system and adjusts the interval between two consecutive frequencies based on the system utilization to reduce the number of frequency change. This algorithm saves the power consumption about 10 to 25 percent compared to a CC RT-DVS method and a frequency-smoothing method.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5191-5211
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• 2016

It is essential to satisfy class-specific QoS constraints to provide broadband services for new generation networks. The present study proposes a QoS-driven multicast scheme for wireless networks in which the transmission rate and end-to-end delay are assumed to be bounded during a multiple multicast session. A distributed algorithm was used to identify a cost-efficient sub-graph between the source and destination which can satisfy QoS constraints of a multicast session. The model was then modified as to be applied for wireless networks in which satisfying interference constraints is the main challenge. A discrete power control scheme was also applied for the QoS-aware multicast model to accommodate the effect of transmission power level based on link capacity requirements. We also proposed random power allocation (RPA) and gradient power allocation (GPA) algorithms to efficient resource distribution each of which has different time complexity and optimality levels. Experimental results confirm that the proposed power allocation techniques decrease the number of unavailable links between intermediate nodes in the sub-graph and considerably increase the chance of finding an optimal solution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.5
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• pp.949-966
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• 2013

Recently, Wireless Body Area Network (WBAN) has promise to revolutionize human daily life. The need for multiple sensors and constant monitoring lead these systems to be energy hungry and expensive with short operating lifetimes. In this paper, we offer a review of existing work of WBAN and focus on energy-aware management in it. We emphasize that nodes computation, wireless communication, topology deployment and energy scavenging are main domains for making a long-lived WBAN. We study the popular power management technique Dynamic Voltage and Frequency Scaling (DVFS) and identify the impact of slack time in Dynamic Power Management (DPM), and finally propose an enhanced dynamic power management method to schedule scaled jobs at slack time with the goal of saving energy and keeping system reliability. Theoretical and experimental evaluations exhibit the effectiveness and efficiency of the proposed method.

• Journal of Electrical Engineering and Technology
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• v.11 no.2
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• pp.480-489
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• 2016

Hidden station problem can occur in power-line communication (PLC) networks. A simple solution to the problem has been proposed to use request-to-send (RTS)/clear-to-send (CTS) exchange, but this approach cannot solve the hidden station problem perfectly. This paper revisits the problem for PLC networks and designs a protocol to solve it. We first analyze the throughput performance degradation when the hidden station problem occurs in PLC networks. Then, we propose an interferer aware multiple access (IAMA) protocol to enhance throughput and fairness performances, which uses unique characteristics of PLC networks. Using the RTS/CTS exchange adaptively, the IAMA protocol protects receiving stations from being interfered with neighboring networks. Through extensive simulations, we show that our proposed protocol outperforms conventional random access protocols in terms of throughput and fairness.

• Journal of Korea Multimedia Society
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• v.13 no.2
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• pp.258-264
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• 2010

In the Ad-hoc networks, the limitation on the availability of power for operation is a significant bottleneck, given the requirements of portability, weight, and size of mobile devices. Hence, the use of routing metrics that consider the capabilities of the power sources of the network nodes contributes to the efficient utilization of energy. This paper presents a QoS routing protocol that minimize the power consumed by a packet in traversing from source node to the destination node. Results obtained of simulation show that, with our approach we can reduce the power consumption of nodes and increases the life time of the network.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.