• Title/Summary/Keyword: pixel circuit

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Novel Priming Discharge Overtopping with Display Period Technique for the Plasma Display Panels (플라즈마 디스플레이 패널의 새로운 표시기간 중첩 프라이밍 방전 기술)

  • Ryeom, Jeong-Duk
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.21 no.8
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    • pp.27-33
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    • 2007
  • A novel priming discharge technique in which the ramp shaped priming pulse is superposed on the sustain period so that the entire plasma display panel (PDP) is discharged at the same time with a single drive circuit is proposed. From the experimental results, it is ascertained that the priming discharge is ignited only in a pixel in which sustain discharge does not occur and it has been understood that the priming pulse hardly influences the sustain discharge. Moreover, high-speed driving with address pulse widths of 0.7[${\mu}s$] was achieved and a wide address voltage margin of 40[V] was obtained by using the drive method applied the proposed priming discharge technique. In these results, full-HDTV PDP with 1080 horizontal scanning lines can be driven without decreasing the brightness and the possibility of the commercializing is also high because this technology is designed for using the commercialized driver IC.

Three-dimensional Geometrical Scanning System Using Two Line Lasers (2-라인 레이저를 사용한 3차원 형상 복원기술 개발)

  • Heo, Sang-Hu;Lee, Chung Ghiu
    • Korean Journal of Optics and Photonics
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    • v.27 no.5
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    • pp.165-173
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    • 2016
  • In this paper, we propose a three-dimensional (3D) scanning system based on two line lasers. This system uses two line lasers with different wavelengths as light sources. 532-nm and 630-nm line lasers can compensate for missing scan data generated by geometrical occlusion. It also can classify two laser planes by using the red and green channels. For automatic registration of scanning data, we control a stepping motor and divide the motor's rotational degree of freedom into micro-steps. To this end, we design a control printed circuit board for the laser and stepping motor, and use an image processing board. To compute a 3D point cloud, we obtain 200 and 400 images with laser lines and segment lines on the images at different degrees of rotation. The segmented lines are thinned for one-to-one matching of an image pixel with a 3D point.

Realization of a High Precision Inspection System for the SOP Types of ICs (SOP형 IC의 고 정밀 외관검사 시스템 구현)

  • Tae Hyo Kim
    • Journal of the Institute of Convergence Signal Processing
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    • v.5 no.2
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    • pp.165-171
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    • 2004
  • Owing to small sizes and high density to the semiconductor It, it is difficult to discriminate the defects of ICs by human eyes. High precision inspection system with computer vision is essentially established for the manufacturing process due to the variety of defective parts. Especially it is difficult to implement the algorithm for the coplanarity of IC leads. Therefore in this paper, the inspection system which can detect the defects of the SOP types of ICs having 1cm${\times}$0.5cm of the chip size is implemented and evaluated it's performance. In order to optimally detect various items, some principles of geometry are theoretically presented , length measurement, pitch measurement, angle measurement, brightness of image and correcton of position. The interface circuit is designed for implementation of inspection system and connected the HANDLER. In the result, the system could detect two ICs' defects per second and confirmed the resolution of 20$\mu$m per pixel.

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FPGA-based Implementation of Fast Histogram Equalization for Image Enhancement (영상 품질 개선을 위한 FPGA 기반 고속 히스토그램 평활화 회로 구현)

  • Ryu, Sang-Moon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.23 no.11
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    • pp.1377-1383
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    • 2019
  • Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

Creation of Actual CCTV Surveillance Map Using Point Cloud Acquired by Mobile Mapping System (MMS 점군 데이터를 이용한 CCTV의 실질적 감시영역 추출)

  • Choi, Wonjun;Park, Soyeon;Choi, Yoonjo;Hong, Seunghwan;Kim, Namhoon;Sohn, Hong-Gyoo
    • Korean Journal of Remote Sensing
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    • v.37 no.5_3
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    • pp.1361-1371
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    • 2021
  • Among smart city services, the crime and disaster prevention sector accounted for the highest 24% in 2018. The most important platform for providing real-time situation information is CCTV (Closed-Circuit Television). Therefore, it is essential to create the actual CCTV surveillance coverage to maximize the usability of CCTV. However, the amount of CCTV installed in Korea exceeds one million units, including those operated by the local government, and manual identification of CCTV coverage is a time-consuming and inefficient process. This study proposed a method to efficiently construct CCTV's actual surveillance coverage and reduce the time required for the decision-maker to manage the situation. For this purpose, first, the exterior orientation parameters and focal lengths of the pre-installed CCTV cameras, which are difficult to access, were calculated using the point cloud data of the MMS (Mobile Mapping System), and the FOV (Field of View) was calculated accordingly. Second, using the FOV result calculated in the first step, CCTV's actual surveillance coverage area was constructed with 1 m, 2 m, 3 m, 5 m, and 10 m grid interval considering the occluded regions caused by the buildings. As a result of applying our approach to 5 CCTV images located in Uljin-gun, Gyeongsnagbuk-do the average re-projection error was about 9.31 pixels. The coordinate difference between calculated CCTV and location obtained from MMS was about 1.688 m on average. When the grid length was 3 m, the surveillance coverage calculated through our research matched the actual surveillance obtained from visual inspection with a minimum of 70.21% to a maximum of 93.82%.

Signal Level Analysis of a Camera System for Satellite Application

  • Kong, Jong-Pil;Kim, Bo-Gwan
    • Proceedings of the KSRS Conference
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    • 2008.10a
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    • pp.220-223
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    • 2008
  • A camera system for the satellite application performs the mission of observation by measuring radiated light energy from the target on the earth. As a development stage of the system, the signal level analysis by estimating the number of electron collected in a pixel of an applied CCD is a basic tool for the performance analysis like SNR as well as the data path design of focal plane electronic. In this paper, two methods are presented for the calculation of the number of electrons for signal level analysis. One method is a quantitative assessment based on the CCD characteristics and design parameters of optical module of the system itself in which optical module works for concentrating the light energy onto the focal plane where CCD is located to convert light energy into electrical signal. The other method compares the design\ parameters of the system such as quantum efficiency, focal length and the aperture size of the optics in comparison with existing camera system in orbit. By this way, relative count of electrons to the existing camera system is estimated. The number of electrons, as signal level of the camera system, calculated by described methods is used to design input circuits of AD converter for interfacing the image signal coming from the CCD module in the focal plane electronics. This number is also used for the analysis of the signal level of the CCD output which is critical parameter to design data path between CCD and A/D converter. The FPE(Focal Plane Electronics) designer should decide whether the dividing-circuit is necessary or not between them from the analysis. If it is necessary, the optimized dividing factor of the level should be implemented. This paper describes the analysis of the electron count of a camera system for a satellite application and then of the signal level for the interface design between CCD and A/D converter using two methods. One is a quantitative assessment based on the design parameters of the camera system, the other method compares the design parameters in comparison with those of the existing camera system in orbit for relative counting of the electrons and the signal level estimation. Chapter 2 describes the radiometry of the camera system of a satellite application to show equations for electron counting, Chapter 3 describes a camera system briefly to explain the data flow of imagery information from CCD and Chapter 4 explains the two methods for the analysis of the number of electrons and the signal level. Then conclusion is made in chapter 5.

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