• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.937-949
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• 1988

This paper proposes a code optimization algorithm for dealing with hazards which are occurred in pipelined architecture due to resource dependence between executed instructions. This algorithm solves timing hazard which results from resource conflict between concurrently executing instructions, and sequencing hazard due to the delay time for branch target decision by reconstructing of instruction sequence without pipeline interlock. The reconstructed codes can be generated efficiently by considering timing hazard and sequencing hazard simultaneously. And dynamic execution time of program is improved by considering structral hazard which can be existed when pipeline is controlled dynamically.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.357-360
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• 2002

This paper is proposed about an efficient pipelined architecture for 3D graphics accelerator to reduce Cache miss ratio. Because cache miss takes a considerable time, about 20∼30 cycle, we reduce cache miss ratio to use pre-fetch. As a result of simulation, we figure out that the miss ratio of cache depends on the size of tile, cache memory and auxiliary cache memory. We can save 6.6% cache miss ratio maximumly.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.746-758
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• 1988

This paper proposes a code scheduling algorithm which gives a software solution to the pipeline interlock. This algorithm provides a heuristic solution by recordering the instructions, instead of using hardware interlock mechanism when pipeline interlock prevents the execution of a machine instruction in a pipelined architecture. Program code size and overall execution time can be reduced due to the increased flexibility in the selection of instructions, which is possible from the alleviated ordering restriction on the use of conflict resources.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.230-238
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• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• Journal of Korea Multimedia Society
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• v.7 no.8
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• pp.1170-1182
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• 2004

A novel 4-way pipelined processing architecture is presented for three-step search block-matching motion estimation. For the 4-way pipelined processing, we have developed a method which divides the current block and search area into 4 subregions respectively and processes them concurrently. Also, we have developed memory partitioning method to access pixel data from 4 subregions concurrently without memory conflict. The architecture has been designed and simulated with C language and VHDL. Experimental results show that the proposed architecture achieves a high performance for real time motion estimation.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.254-256
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• 2000

본 논문에서는 여러 단계의 QoS(Quality of Service)를 지원하면서 빠르고 확장이 용이하며 각종 패킷 폐기(packet drop) 방식을 지원하는 평형 파이프라인 우선순위 아웃풋 큐 구조(balanced pipelined priority output queue architecture)를 제시하고 있다. 본 방안은 기존에 연구된 파이프라인 우선순위 힙(pipelined heap, P-heap)[1]을 기반으로 하고 있다. 파이프라인 우선순휘 힙은 우선순위에 따라 패킷을 전송하는 작업을 파이프라인 방식으로 처리하여 처리 성능을 향상시킨 아웃풋 큐 구조이다. 그러나 P-heap은 평형성(balance) 문제를 전혀 고려하고 있지 않으며, 다양한 패킷 폐기 방안을 제공하고 있지 못하다. 본 논문에서는 이런 측면에서 P-heap을 개선한 Advanced P-heap을 제안하고 있다. Advanced P-heap은 평균적인 상황에서 힙에 평형성을 부여하고, 각종 패킷 폐기 정책을 지원할 수 있는 일반적인 우선순위별 차별 패킷 구조를 제시하고 있다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.790-794
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• 2007

This paper presents a new index mapping method for DFT (Discrete Fourier Transform) and its application to multidimensional DFT. Unlike conventional index mapping methods such as DIT (Decimation in Time) or DIF (Decimation in Frequency) algorithms, the proposed method is based on two levels of decomposition and it can be very efficiently used for implementing multidimensional DFT as well as 1-dimensional DFT. The proposed pipelined architecture for multidimensional DFT is very flexible so that it can lead to the best tradeoff between performance and hardware requirements. Also, it can be easily extended to higher dimensional DFTs since the number of CEs (Computational Elements) and DCs (Delay Commutators) increase only linearly with the dimension. Various implementation options based on different radices and different pipelining depths will be presented.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.212-224
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• 2000

In this paper, a parallel processing system is proposed for improving the processing speed of image related applications. The proposed parallel processing system is fully synchronous SIMD computer with pipelined architecture and consists of processing elements and a multi-access memory system. The multi-access memory system is made up of memory modules and a memory controller, which consists of memory module selection module, data routing module, and address calculating and routing module, to perform parallel memory accesses with the variety of types: block, horizontal, and vertical access way. Morphological filter had been applied to verify the parallel processing system and resulted in faithful processing speed.

• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.1-7
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• 1999

In this research, transformation-based optimization techniques for pipelined designs have been developed. The transformation-based optimization techniques include pipelined architecture transformations and retiming transformations. The new transformation method has the following three features. First, the overall performance of a pipelined system is optimized owing to various transformations including retiming of multiple pipelined blocks. Second, these techniques can be used to search a large solution space by allowing efficient exploration of trade-offs between area and performance. Third, these techniques can be easily extended to a new transformation or algorithm and can be used to optimize memory or bus architectures. Experimental results illustrate that these transformation-based optimization techniques improve area by 21% and performance by 17% on the average for a set of pipelined designs. Especially, the techniques are useful to efficiently explore a large design space.