• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1276-1279
• /
• 2002

In order to satisfy the requirement for various applications in an electronic device, many dynamically reconfigurable systems such as FPGAs have been used recently. This paper presents a pipelined scheduling for dynamically reconfigurable systems based on FPGAs. For reconfigurable systems conventional schedulings have reduced processing time by minimizing the number of reconfigurations. However, they are not effective enough for applications including many iterative processes such as digital signal processing. Our approach has been able to increase throughput of iterative applications on dynamically reconfigurable systems by using pipelined scheduling.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.63-66
• /
• 1999

Echo and near-end crosstalk(NEXT) can be generated in two-wire duplex transmission. In this paper investigates how to cancel echoes of high speed communication. A pipeline algorithm is used to remove the echoes that high speed communication. It is least mean squared(LMS) algorithm based on the relaxed look-ahead concept, is focused on the pipelined LMS, and its performance is compared to that of the serial LMS algorithm. And we design pipelined adaptive filtering. In advanced of the hardware implementation with VHDL code the performance of pipelined LMS algorithm is verified by the computer simulation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.4
• /
• pp.227-233
• /
• 2006

In order to reduce blocking artifacts and improve compression efficiency, H.264/AVC standard employs an adaptive in-loop deblocking filter. This paper proposes a new hardware architecture of the deblocking filter that employs a four-stage pipelined structure with an efficient data distribution. The proposed architecture allows a simultaneous supply of eight data samples to fully utilize the pipelined filter in both horizontal and vertical filterings. This paper also presents a new filtering order and data reuse scheme between consecutive macroblock filterings to reduce the communication for external memory access. The number of required cycles for filtering one macroblock (MB) is 357 cycles when the proposed filter uses dual port SRAMs. This execution speed is only 41.3% of that of the fastest previous work.

• Journal of Internet Computing and Services
• /
• v.7 no.1
• /
• pp.49-57
• /
• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

• Proceedings of the Korean Information Science Society Conference
• /
• 2004.04a
• /
• pp.67-69
• /
• 2004

본 논문은 Grid상의 workflow 시스템인 Workflow based Grid Portal for PSE(이하 WISE)를 이용한 인공 심장의 3차원 병렬 volume rendering system 디자인과 구현에 대하여 기술한다. Grid는 전 세계에 분산되어 있는 고성능, 대용량 자원들을 고속 네트워크로 연동하여 사용할 수 있게 하는 환경이며, WISE 시스템은 workflow 개념을 도입하여, 이런 자원들의 효율적이고 편리하게 관리해주고 아울러 여러 가지 패턴을 이용해 프로그래밍 할 수 있게 해주는 middleware이다. 본 논문에서는 Grid 상에서 WISE system에서 제공하는 프로그래밍 패턴을 이용하여 구조화되어 있지 않은 인공심장 데이터를 병렬 processing Pipeline 모델을 바탕으로 효율적인 parallel 3차원 가시화를 하기 위한 parallel pipelined volume rendering system을 구현하였다.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.533-536
• /
• 2000

In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.6
• /
• pp.718-727
• /
• 2014

In a wireless communications system, a predistorter is often used to compensate for the nonlinear distortions that result from operating a power amplifier near the saturation region, thereby improving system performance and increasing the spectral efficiency for the communication channels. This paper presents a new VLSI design for the polynomial digital predistorter (DPD). The proposed DPD uses a Coordinate Rotation Digital Computing (CORDIC) processor and a PD process with a fully-pipelined architecture. Due to its simple and regular structure, it can be a competitive design when compared to existing polynomial-type and approximated DPDs. Implementing a fifth-order distorter with the proposed design requires only 43,000 logic gates in a $0.35{\mu}m$ CMOS standard cell library.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.6
• /
• pp.49-57
• /
• 1993

In the paper, we describe the design of a pipelined datapath synthesis system for DSP applications. Taking SFG (Signal Flow Graph) in schematic as inputs, the system generates pipelined datapaths automatically through scheduling and module allocation processes. For efficient hardware synthesis, scheduling and module allocation algorithms are proposed. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equi-distribution of operations to partitions is adopted as the objective function. Module allocation is performed to reduce the interconnection cost from the initial allocation. In the experiment, we compare the results with those of other systems and show the effectiveness of the proposed algorithms.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.5
• /
• pp.475-480
• /
• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.05a
• /
• pp.693-694
• /
• 2014

This paper proposes a new pipelined dynamic bandwidth allocation algorithm for XG-PON (10-Gbps-capable passive optical network) passive optical networks) system. The pipelined algorithm is used when a dynamic bandwidth allocation algorithm cannot finished in an unit time. In the proposed mechanism, the request is immediately transferred to each pipeline block to improve performance.