• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.59-62
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• 2000

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. From now on, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e., write \longrightarrow refresh \longrightarrow read). Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• 한국정보과학회논문지:시스템및이론
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• 제35권6호
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• pp.248-262
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• 2008

대용량 멀티미디어 파일의 증가와 개인의 디지털 정보의 중요성이 날로 증가하면서 저장장치는 고용량화, 고집적화 되는 방향으로 발전하고 있다. 따라서 저장장치에 발생되는 물리적인 오류는 단순히 작은 영역의 손상이 아닌 매우 넓은 영역에 대한 정보 손실로 이어진다. 이를 방지하기 위해서는 시스템을 사용하기 전에 물리적인 오류에 대한 시스템의 강인성과 대처 수준을 검증하고 사용해야 한다. SOAR(Storage Reliability Analyzer)는 검증의 핵심이 될 수 있는 물리적인 오류 발생 기능과 복구 기능을 가지고 있으며 이것은 시스템에 대한 신뢰성과 강인성을 검증 할 수 있는 유용한 도구이다. 이 기능을 보다 편리하게 사용하기 위해서 SOAR는 3가지의 특수한 오류 적용 기법과 파일시스템에 특화된 2가지 기법을 가지고 있다. 본 논문에서는 SOAR를 이용해서 어플리케이션부터 파일시스템까지 물리적인 오류에 대한 검증을 실제 수행하고 결과 분석을 진행하였다. 그러므로 SOAR는 물리적인 오류에 대한 시스템의 많은 문제점을 발견하였고 동시에 그 기능을 증명하였다.

• 전기전자학회논문지
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• 제5권1호
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• pp.43-51
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• 2001

메모리의 집적도가 올라갈수록 원치 않는 셀간의 간섭과 동시에 bit-line간의 상호 노이즈도 증가하게 된다. 그리고 높은 고장 검출율을 요구하는 고집적 메모리의 테스트는 많은 테스트 백터를 요구하게 되거나 비교적 큰 추가 테스트 회로를 요구하게 된다. 지금까지 기존의 테스트 알고리즘은 이웃 bit-line의 간섭이 아니라 이웃 셀에 중점을 두었다. 본 논문에서는 NPSFs(Neighborhood Pattern Sensitive Faults)를 기본으로 한 NBLSFs(Neighborhood Bit-Line Sensitive Faults)를 위한 새로운 테스터 알고리즘을 제안한다. 그리고 제안된 알고리즘은 부가 회로를 요구하지 않는다. 메모리 테스트를 위해 기존의 5개의 셀 레이아웃이나 9개의 셀 레이아웃을 사용하지 않고 NBLSF 검출에 최소한 크기인 3개의 셀 레이아웃을 이용하였다. 더구나 이웃 bit-line에 의한 최대의 상호잡음을 고려하기 위해 테스트 동작에 refresh 동작을 추가하였다(예 $write{\rightarrow}\;refresh{\rightarrow}\;read$). 또한 고착고장, 천이고장, 결합고장, 기존의 pattern sensitive 고장, 그리고 이웃 bit-line sensitive 고장 등도 검출될 수 있음을 보여준다.

• 대한전자공학회논문지SD
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• 제40권4호
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• pp.74-84
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• 2003

기존의 테스트 알고리즘은 대부분 셀간의 고장에 중심이 맞추어져 있어 메모리의 집적도의 증가와 더불어 일어나는 word-line 과 bit-line 결합 잡음에 의한 고장을 효과적으로 테스트 할 수 없다 본 논문에서는 word-line 결합 capacitance에 의한 고장의 가능성을 제시하고 새로운 고장 모델인 WLSFs(Word-Line Sensitive Faults)을 제안하였다. 또한 word-line 과 bit-line 결합 잡음을 동시에 고려한 알고리즘을 제시하여 고장의 확률을 높였고 고장의 원인을 기존의 고장 모델로는 되지 않음을 보여준다. 제안된 알고리즘은 기존의 기본적인 고장인 고착고장, 천이고장, 그리고 결합고장을 5개의 이웃셀 내에서 모두 검출할 수 있음을 보여준다.

• ETRI Journal
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• 제26권6호
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• 한국철도학회:학술대회논문집
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• 한국철도학회 1998년도 창립기념 춘계학술대회 논문집
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• pp.408-418
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• 1998

This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.

• Nuclear Engineering and Technology
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• 제29권6호
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• pp.433-443
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• 1997

In this work, an analytic approach to the dependability of software in the operational phase is suggested with special attention to the hardware fault effects on the software behavior : The hardware faults considered are memory faults and the dependability measure in question is the reliability. The model is based on the simple reliability theory and the graph theory which represents the software with graph composed of nodes and arcs. Through proper transformation, the graph can be reduced to a simple two-node graph and the software reliability is derived from this graph. Using this model, we predict the reliability of an application software in the digital system (ILS) in the nuclear power plant and show the sensitivity of the software reliability to the major physical parameters which affect the software failure in the normal operation phase. We also found that the effects of the hardware faults on the software failure should be considered for predicting the software dependability accurately in operation phase, especially for the software which is executed frequently. This modeling method is particularly attractive for the medium size programs such as the microprocessor-based nuclear safety logic program.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1996년도 춘계학술발표회논문집(2)
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• pp.725-730
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• 1996

In this work, the software behavior under memory faults in operation phase is modeled and simulated using the stochastic activity network, generalized stochastic Petri nets. This networks permit the representation of concurrency, timeliness, fault tolerance, and degradable performance of system and provide a means for determining the stochastic behavior of a complex system. We estimate the reliability of an application software in the digitized system in nuclear power plants and show the sensitivity of the software reliability to the major physical parameters which affect the software failure in normal operation phase. We found that the effects of the hardware faults on the software failure should be considered for predicting the software dependability accurately in operation phase.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1998년도 추계학술대회 학술발표 논문집
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• pp.447-452
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• 1998

A fault is considered as a variation of physical parameters; therefore the design of fault detection and identification(FDI) can be reduced to the parameter identification of a non linear system and to the association of the set of the estimated parameters with the mode of faults. ANFIS(Adaptive Neuro-Fuzzy Inference System) which contains multiple linear models as consequent part is used to model non linear systems. In this paper, we proposes an FDI system for non linear systems using ANFIS. The proposed diagnositc system consists of two ANFISs which operate in two different modes (parallel-and series-parallel mode). It generates the parameter residuals associated with each modes of faults which can be further processed by additional RBF (Radial Basis function) network to identify the faults. The proposed FDI scheme has been tested by simultation on a two-tank system

• 한국농공학회지
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• 제43권1호
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• pp.106-115
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• 2001

This study attempted to make evaluation model of deterioration for the rural house. defined the deterioration of rural house as the two categories. First is the physical deterioration which is affected by physical faults and the second is the social deterioration which is affected by change of environments. As a results, physical deterioration model was developed by types of rural house, and social deterioration model was considered to reverse function of satisfaction of a resident.