• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.260-264
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• 2017

Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

• 한국인쇄학회지
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• 제28권1호
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• pp.51-63
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• 2010

Ink-jet is part of the non impact printing that shooting the ink drop from the nozzle to paper. It is very silence and express good color. There are two types of printing that continuous and drop on demand. But drop on demand process is becoming the mainstream. these days, LCD, PDP is passed more than semiconductor industry. And we expect organic EL, FED as a next display. But product equipment, main component and technology have a gap between an advanced country and us nevertheless physical development. Expecially, previous process part is depended on imports. Ink-jet printing technology that there isn't complicated photo lithography process is attracted, so ink-jet printing resolution is more embossed. But there were not many of ink-jet resolution thesis but ink-jet head or nozzle. Because, to out of the ink from the nozzle is unseeable and hard to experiment. Therefore this thesis was experimented and simulated how can ink-jet printer improved resolution by flow-3d simulation package program.

• 한국정밀공학회지
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• 제22권1호
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• pp.199-206
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• 2005

Mask manufacturing is a high COC and COO process in developing of semiconductor devices because of mask production tool with high resolution. Direct writing has been thought to be the one of the patterning method to cope with development or small-lot production of the device. This study consists two categories. One is the additional process of the direct and maskless patterning generation using SLA for easy and convenient application and the other is a removal process using wet-etching process. In this study, cured status of epoxy pattern is most important parameter because of the beer-lambert law according to the diffusion of UV light. In order to improve the contact force between patterns and substrate, prime process was performed and to remove the semi-cured resin which makes a bad effects to the pattern, spin cleaning process using TPM was also performed. At a removal process, contact force between photo-curable resin as an etching mask and Si wafer is important parameter.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.310-313
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• 2002

Structures obtained with a direct boning of two FZ silicon wafers joined in such a way that a smooth surface of one wafer was attached to the grooved surface of the other were studied. A square net of grooves was made with a conventional photo lithography process. After high temperature annealing the appearance of voids and the rearrangement of structural defects were observed with X-ray diffraction topography techniques. It was shown that the formation of void free grooved boundaries was feasible. In the cases when particulate contamination was prevented, the voids appeared in the grooved structures could be eliminated with annealing. Since it was found that the flattening was accompanied with plastic deformation, this deformation was suggested to be intensively involved in the process of void removal. A model was proposed explaining the interaction between the structural defects resulted in "a dissolution" of cavities. The described processes may occur in grooved as well as in smooth structures, but there are the former that allow to manage air traps and undesirable excess of dislocation density. Grooves can be paths for air leave. According to the established mechanisms, if not outdone, the dislocations form local defect arrangements at the grooves permitting the substantial reduction in defect density over the remainder of the interfacial area.

• 한국세라믹학회지
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• 제47권6호
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• pp.623-626
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• 2010

We synthesized ZnO nanowires patterned on Si substrate and investigated the field emission properties of the nanowires. Firstly, Au catalyst layers were fabricated on Si substrate by photo-lithography and lift-off process. The diameter of Au pattern was $50\;{\mu}m$ and the pattern was arrayed as $4{\times}4$. ZnO nanowires were grown on the Au catalyst pattern by the aid of Au liquid phase. The orientation of the ZnO nanowires was vertical on the whole. Sufficient brightness was obtained when the electric field was $5.4\;V/{\mu}m$ and the emission current was $5\;mA/cm^2$. The threshold electric field was $5.4\;V/{\mu}m$ in the $4{\times}4$ array of ZnO nanowires, which is quite lower than that of the nanowires grown on the flat Si substrate. The lower threshold electric field of the patterned ZnO nanowires could be attributed to their vertical orientation of the ZnO nanowires.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.419-419
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• 2014

Interdigitated nanogap device (IND) is an attractive tool for biomolecular detection due to its huge on-off signal ratio, great tolerance to the variation in biochemical environment, and relatively simple implementation processes. Here, we report on the IND-based detection of Influneza A virus by sandwich immunoassay. The INEs were fabricated by photo lithography followed by the in-house chemical lithographic technique for the narrowing the initial gap distance. The surface of the silicon oxide between the two gold electrodes was chemically modified to immobilize primary antibodies for the immuno-specific interaction with the influenza A virus antigen. After immersing the functionalized-IND into the sample solution containing the influenza A virus, the device was exposed to the secondary antibody conjugated Au nanoparticles (Au NPs). The INDs showed a huge jump in the electric conductance when the sample solution contained the influenza A virus of the concentration as low as 10 ng/mL. We hope that this IND-based sensing can be applied to the development of simple and reliable diagnostic means of influenza viruses.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2007년 추계학술발표대회 개요집
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• pp.235-237
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• 2007

In this paper, fabrication of Sn-3.0Ag-0.5Cu solder bumping having accurate composition and behavior of intermetallic compounds(IMCs) growth at interface between Sn-Ag-Cu bumps and Cu substrate were studied. The ternary alloy of the Sn-3.0Ag-0.5Cu solder was made by two binary(Sn-Cu, Sn-Ag) electroplating on Cu pad. For the manufacturing of the micro-bumps, photo-lithography and reflow process were carried out. After reflow process, the micro-bumps were aged at $150^{\circ}C$ during 1 hr to 500 hrs to observe behavior of IMCs growth at interface. As a different of Cu contents(0.5 or 2wt%) at Sn-Cu layer, behavior of IMCs was estimated. The interface were observed by FE-SEM and TEM for estimating of their each IMCs volume ratio and crystallographic-structure, respectively. From the results, it was found that the thickness of $Cu_3Sn$ layer formed at Sn-2.0Cu was thinner than the thickness of that layer be formed Sn-0.5Cu. After aging treatment $Cu_3Sn$ was formed at Sn-0.5Cu layer far thinner.

• 반도체디스플레이기술학회지
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• 제9권4호
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• pp.25-29
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• 2010

We have investigated the effect of surface roughness of TCO substrate on the characteristics of OLED (organic light emitting diodes) devices. In order to control the surface roughness of AZO thin films, we have processed photo-lithography and reactive ion etching. The micro-size patterned mask was used, and the etching depth was controlled by changing etching time. The surface morphology of the AZO thin film was observed by FESEM and atomic force microscopy (AFM). And then, organic materials and cathode electrode were sequentially deposited on the AZO thin films. Device structure was AZO/${\alpha}$-NPD/DPVB/$Alq_3$/LiF/Al. The DPVB was used as a blue emitting material. The electrical characteristics such as current density vs. voltage and luminescence vs. voltage of OLED devices were measured by using spectrometer. The current vs. voltage and luminance vs. voltage characteristics were systematically degraded with increasing surface roughness. Furthermore, the retention test clearly presented that the reliability of OLED devices was directly influenced with the surface roughness, which could be interpreted in terms of the concentration of the electric field on the weak and thin organic layers caused by the poor step coverage.

• 한국산업보건학회지
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• 제22권1호
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• pp.52-59
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• 2012

Objectives: The purpose of this study was to evaluate the exposure possibility of by-products during the semiconductor manufacturing processes. Methods: The authors investigated types of chemicals generated during semiconductor manufacturing processes by the qualitative experiment on generation of by-products at the laboratory and a literature survey. Results: By-products due to decomposition of photoresist by UV-light during the photo-lithography process, ionization of arsine during the ion implant process, and inter-reactions of chemicals used at diffusion and deposition processes can be generated in wafer fabrication line. Volatile organic compounds (VOCs) such as benzene and formaldehyde can be generated during the mold process due to decomposition of epoxy molding compound and mold cleaner in semiconductor chip assembly line. Conclusions: Various types of by-products can be generated during the semiconductor manufacturing processes. Therefore, by-products carcinogen such as benzene, formaldehyde, and arsenic as well as chemical substances used during the semiconductor manufacturing processes should be controlled carefully.