• Science of Emotion and Sensibility
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• v.16 no.4
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• pp.527-534
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• 2013

In this study, we analyzed spatial-frequency relationship related brain function for change of the time during attentional visual stimulus through the analysis of Coherence. With experimentation about ERP(Event Related Potential)data, it revealed that change of the phase synchronization between different scalp locations at ${\theta}$, ${\alpha}$ band. ERP between left and right frontal lobes, between the frontal and central lobes showed the phase synchronization at the P100, N200, ERP between the frontal and occipital lobes showed the phase synchronization at the P300 related information of visual stimulus. Compared to STFT using the window of a fixed length, CWT is able to multi-resolution analysis with the adjustment of parameters of mother wavelet. Thus, coherence results with CWT was found to be effective for analysis of time-varying spatial-frequency relationship in ERP. The phase synchronization for inattentional visual stimulus was not observed.

• Proceedings of the Korean Society for Cognitive Science Conference
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• 2010.05a
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• pp.37-41
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• 2010

The previous investigations of electroencephalogram (EEG) activity in the memory retrieval tasks demonstrated that event-related potentials (ERP) during recollection showed different durations and the peak levels from those without recollection. However, it has been unknown that recollection in memory retrieval also modulates high-frequency brain rhythms as well as establishes large-scale synchronization across different cortical areas. In this study, we examined the spectral components of the EEG signals, especially the gamma bands (20-80Hz), measured during the memory retrieval tasks. Specifically, we focused on two major spectral components: first, we evaluated the temporal patterns of the power spectral density before and after the onset of the memory retrieval task; second, we estimated phase synchrony between all possible pairs of EEG channels to evaluate large-scale synchronization. Fourteen healthy subjects performed the memory retrieval task in the virtual reality environment where they selected whether or not t he present item was seen in the previous training period. When the subjects viewed the unseen items, the middle gamma power (40-60Hz) appeared to increase 200-500ms after stimulus onset while the low gamma power (20Hz) was suppressed all the way through the post-stimulus period 150ms after onset. The degree of phase synchronization in this low gamma level, however, increased when the subjects fetched the item from memory. This suggests that phase synchrony analysis might reveal different aspects of the memory retrieval process than the gamma power, providing additional information to the inference on the brain dynamics during memory retrieval.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.26-33
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• 1992

This paper describes a new phase-difference detection method and the associate process algorithm for calculating the mean value of phase difference detected and OVCXO control value and for monitoring and controlling the DP-PLL operation status to be used in the design of a high-frequency DP-PLL. Through the experiments of DP-PLL implemented with 16-bit processor, memories, pheriperals and OVCXO to eraluate the suggested method and algorithm, it is shown that a remarkable improvement in PLL function such as phase detection, and reference clock tracing capability, jitter absorbability and frequency stability compared with other existing DP-PLL synchronization device is achieved.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.6
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• pp.447-452
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• 2008

In the paper, the product-type PLL system, which is so suitable for synchronizing a single phase grid voltage is designed. The PLL system is modelled with the small signal analysis. Both the cut-off frequency of low pass filter and the optimal gain are derived by considering the transient response for synchronization as well as a distortion of synchronization signal. Through the simulation studies and experimental results, the transient response and ripple component of synchronization signal are investigated with a variation of both the cut-off frequency and gain in order to verify the performance of design.

• The KIPS Transactions:PartC
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• v.16C no.5
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• pp.637-644
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• 2009

A study about performance analysis of synchronization clock using measured clock noises is required. Therefore this paper executed the study for performance analysis of synchronization clock and acquirement of maximum number of network node with various clock states using measured clock noises in NG-SDH networks. Also this paper generated a suitable clock model using measured clock noises, and carried out simulations with various clock states. Through the simulation results, maximum numbers were 80 or more network nodes in normal state, and were below 37 nodes in short-term phase transient(SPT) state, and were 50 or more in long-term phase transient(LPT) state. Accordingly this study showed that maximum numbers to meet ITU-T specification were below 37 network nodes in three clock states. Also this study showed that when SPT or LPT states occur from NE network before DOTS system, synchronization source must change with other stable synchronization source of normal state.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.7-8
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• 2017

The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.72-80
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• 2015

In distributed generation systems, a grid-connected inverter should operate with synchronization to grid voltage. Considering that synchronization requires the phase angle of grid voltage, a phase locked loop (PLL) scheme is often used. The synchronous reference frame phase locked loop (SRF-PLL) is generally known to provide reasonable performance under ideal grid voltage. However, this scheme indicates performance degradation under the harmonic distorted or unbalanced grid voltage condition. To overcome this limitation, this paper proposes a phase and harmonic detection method of grid voltage using fast Fourier transform (FFT). To reduce the calculation time of FFT algorithm, minimum sampling data is taken from the voltage measurement to determine the phase angle and the magnitude of harmonic components. An experimental test setup for a grid-connected inverter system has been constructed. By comparative simulations and experiments under various abnormal grid voltage conditions, the proposed scheme has been proven to effectively track the phase angle of the grid voltage.

• Journal of Power Electronics
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• v.15 no.1
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• pp.216-226
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• 2015

Grid synchronization is one of the key techniques for the grid-connected power converters used in distributed power generation systems. In order to achieve fast and accurate grid synchronization, a new phase locked loop (PLL) is proposed on the basis of the complex filter matrixes (CFM) orthogonal signal generator (OSG) crossing-decoupling method. By combining first-order complex filters with relation matrixes of positive and negative sequence voltage components, the OSG is designed to extract specific frequency orthogonal signals. Then, the OSG mathematical model is built in the frequency-domain and time-domain to analyze the spectral characteristics. Moreover, a crossing-decoupling method is suggested to decouple the fundamental voltage. From the eigenvalue analysis point of view, the stability and dynamic performance of the new PLL method is evaluated. Meanwhile, the digital implementation method is also provided. Finally, the effectiveness of the proposed method is verified by experiments under unbalanced and distorted grid voltage conditions.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.81-86
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• 2010

Since CORDIC (COordinate Rotation DIgital Computer) is able to carry out the phase operation, such as vector to phase conversion or rotation of vectors, with adders and shifters, it is well suited for the design of the frequency synchronization unit in OFDM receivers. It is not easy, however, to fully utilize the CORDIC in the OFDM demodulator because of the non-linear characteristics of the direction sequence (DS), which is the representation of the phase in CORDIC. In this paper a new representation method is proposed to linearize the direction sequence approximately. The maximum phase error of the linearized binary direction sequence (LBDS) is also discussed. For the purpose of designing the hardware, the architectures for the binary DS (BDS) to LBDS converter and the LBDS to BDS inverse converter are illustrated. Adopting LBDS, the overall frequency synchronization hardware for OFDM receivers can be implemented fully utilizing CORDIC and general arithmetic operators, such as adders and multipliers, for the phase estimation, loop filtering of the frequency offset, derotation for the frequency offset correction. An example of the design of 22 bit LBDS for the T-DMB demodulator is also presented.