• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.11
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• pp.945-951
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• 2021

The SOQPSK-TG is a modulated signal for aeronautical telemetry with a very good bandwidth efficiency. In this paper, the frequency waveform filter of the SOQPSK-TG is linearly approximated and modeled with a duobinary precoder and a modified frequency waveform filter having a phase transition period of about 1T_b. In combination with the existing precoder, the SOQPSK-TG is modeled by a double duobinary MSK. Comparing the SOQPSK-TG signal and the newly modeled double duobinary MSK signal in time domain and frequency domain, it is confirmed that the two signals are almost identical and there is virtually no performance difference. Moreover, we can attain 0.1 dB BER performance improvement compared to the existing cosine filter when the filter of the IQ-detector is implemented with a cosine sum filter taking into account the change in the modulation index by the new double doubinary precoder.

• Journal of information and communication convergence engineering
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• v.22 no.2
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• pp.89-97
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• 2024

This research conducted a comparative analysis of two communication systems. The first system utilizes a conventional series configuration consisting of a symbol-rate least mean square (LMS) equalizer followed by a timing recovery loop. The second system introduces an innovative approach that integrates a symbol-rate LMS equalizer and a timing recovery component within a single loop, allowing mutual feedback between the two blocks. In this integrated system, the equalizer also provides timing error information, thereby eliminating the requirement for a separate threshold error detector. This study examines the performance curves of both system configurations. The simulation results revealed that the integrated system may offer improved stability in terms of multiple transmission challenges, including phase and frequency offsets and intersymbol interference. Further analysis and discussion highlight the significant insights and implications of the proposed architecture. Overall, the present findings provide an alternative perspective on the joint implementation of equalization and timing recovery in communication systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1848-1857
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• 2001

This paper proposes the ETEO and MTEO burst signal detector based on TEO algorithm. These algorithms must be used after STR and AGC operation, but are not related to phase and frequency offset. ETEO algorithm is extended version of original TEO, and MTEO algorithm is proposed for improving the output characteristics of ETEO. Also, modified ETEO and MTEO algorithm are proposed for detection of PREAMBLE64. Optimal threshold value is determined and miss and false alarm probability and FER performance are evaluated by computer simulation. Finally, this paper proposes MTEO algorithm with M=3 to guarantee the Performance that FER is less than 10$\^$-2/.

• Journal of Biomedical Engineering Research
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• v.7 no.2
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• pp.139-146
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• 1986

Pulsed ultrasonic Doppler system is a useful diagnostic instrument to measure blood-flow-velocity, velocity profile, and volume-blood-flow. This system is more powerful compare with 2-dimensional B-scan tissue image. A system has been deve- loped and ii being evaluated using TMS 32010 DSP. We use this DSP for the purpose of real-time spectrum analyzer to obtain spectrogram in singlegate pulsed Doppler system and for the serial comb filter to cancel clutter and zero crossing counter to estimate Doppler mean frequency in multigate pulsed Doppler system. The Doppler shift of the backscattered signals is sensed in a phase detector. This Doppler signal corresponds to the mean velocity over a some region in space defined by the ultrasonic beam dimensions, transmitted pulse duration, and transducer ban(iwidth. Multi- gate pulsed Doppler system enable the transcutaneous and simultaneous assessment of the velocities in a number of adjacent sample volumes as a continuous function of time. A multigate pulsed Doppler system processing the information originating from presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.185-192
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• 2013

In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7, and 5.4 Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit covers three different operating frequencies with a single VCO switching the operating frequency by the 3-bit digital code. The prototype chip has been designed and verified using a 65 nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4 Gbps at $2^{31}$-1 PRBS is measured to 7/5.6/4.7 $ps_{rms}$, respectively, while consuming 11 mW from a 1.2 V supply.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.05a
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• pp.336-340
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• 2003

The frame synchronization should be acquired before performing other data-aided receiving algorithms, such as data-aided channel equalizing, beam-forming and phase, symbol timing, and frequency synchronizing, since all of them are using preamble or training sequence to estimate the amount of error from the received signal. In this paper, we present a new frame synchronization scheme for underwater ultrasonic image burst transmission system, which computes the correlation between received symbol sequence and one CAZAC sequence, composed of the latter half of the first CAZAC sequence of preamble and the first half of the second CAZAC sequence of preamble and then compares a threshold value. If the correlation value is bigger than the threshold value, the frame detector determines that the frame synchronization is achieved at that sample.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2184-2186
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• 2001

The research presented in this paper focuses on a method for the detection of High Impedance Fault(HIF). The method will use the fast wavelet transform and neural network system. HIF on the multi-grounded three-phase four-wires primary distribution power system cannot be detected effectively by existing over current sensing devices. These paper describes the application of fast wavelet transform to the various HIF data. These data were measured in actual 22.9kV distribution system. Wavelet transform analysis gives the frequency and time-scale information. The neural network system as a fault detector was trained to discriminate HIF from the normal status by a gradient descent method. The proposed method performed very well by proving the right state when it was applied staged fault data and normal load mimics HIF, such as arc-welder.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.56-63
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• 2008

This paper describes a 12 bit 1GS/s current mode segmented DAC for WCDMA communication. The proposed circuit in this paper employes segmented structure which consists of 4bit binary weighted structure in the LSB and 4bit thermometer decoder structure in the mSB and MSB. The proposed DAC uses delay time compensation circuits in order to suppress performance decline by delay time in segmented structure. The delay time compensation circuit comprises of phase frequency detector, charge pump, and control circuits, so that suppress delay time by binary weighted structure and thermometer decoder structure. The proposed DAC uses CMOS $0.18{\mu}m$ 1-poly 6-metal n-well process, and measured INL/DNL are below ${\pm}0.93LSB/{\pm}0.62LSB$. SFDR is approximately 60dB and SNDR is 51dB at 1MHz input frequency. Single DAC's power consumption is 46.2mW.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.