• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.546-550
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• 2013

We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.

• 전자공학회논문지A
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• 제32A권7호
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• pp.51-57
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• 1995

The theoretical analysis for AlInAs/GaInAs resonant tunneling diodes (RTDs), which have shown the improved negative differential resistance (NDR) characteristics, has scarcely been made in comparison with AlGaAS/GaAs RTDs. In this paper, the static current-voltage relation of Al$_{0.48}In_{0.52}As/Ga_{0.47}In_{0.53}$As RTDs were numerically estimated by using a self-consistent method. Assuming a simplified RTD with single quantum well structure and spacer layers, the peak current density (J$_{P}$) and the peak-to-valley current ratio (PVCR) were analysed as the function of the thickness of the well, the barrier and the spacer layer, and temperature. As the results, the peak current density and the peak-to-valley current ratio indicated a reciprocal relation roughly in respect to the thicknesses of the well and the barrier, and it was theoretically predicted that it be not attainable to provide a high peak current desity (J$_{P}$) over 1${\times}10^{5}A/cm^{2}$ as well as the large peak-to-valley current ratio (PVCR) over 10 that were the the critical conditions for the practical use.

• 한국통신학회논문지
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• 제18권7호
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• pp.1036-1043
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• 1993

대기압 MOCVD방법으로 이중 장벽 구조의 공명 투과 소자를 제작하여 상온과 77K에서의 부저항 특성을 특정하였다. GaAs 양자 우물과 spacer, AIGaAs 장벽을 사용하여 성장온도를 변화시켜 공명 투과 소자를 제작한 결과 상온에서 2.35, 77K에서 15.3의 높은 peak-to-valley 전류비를 얻었다 컴퓨터 모의 실험에서는 coherent 투과만을 고려하여 peak 전류를 계산해서 실험치와 잘 일치하는 것을 알 수 있었다. AlGaAs 장벽에 InGaAs 양자 우물과 spacer를 사용하여 전자의 공급량을 증가시킨 구조에서는 상온에서 8.6KA/cm의 높은 peak 전류와 4.0의 큰 peak-to-valley 전류비를 얻었다.

• 한국진공학회지
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• 제1권1호
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• pp.134-138
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• 1992

GaAs/AlAs 이중장벽 구조를 MBE(Molecular Beam Epitaxy)법으로 성장하여, mesa diode를 제작하고 전류전압 특성을 측정하였다. 계면은 평탄한 이중장벽 구조로 성장 되었음이 확인되었으며, 실온에서 장벽의 두께가 변화함에 따라 PVCR(Peak to Valley Current Ratio)의 값은 크게 변하지 않았다. 이는 장벽의 두께가 증가함에 따라 nonresonant tunneling에 의한 valley current가 크게 증가함에 기인한다.

• 전력전자학회논문지
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• 제23권1호
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• pp.59-65
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• 2018

A new single-stage flyback power converter with PFC for electrolytic capacitor-less LED driver is proposed in this study. This method minimizes the peak-to-average ratio of the LED driving pulsating current by adding the LED driving current near the LED current valley area, as well as the third harmonic component injection into the input current. The reduced peak current value of the LED drive current minimizes the thermal stress of the LED itself, thereby increasing the reliability of the LED, as well as achieving a long lifetime. Simulation and experimental results show the usefulness of the proposed topology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1456-1458
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• 1996

In resonant tunneling diodes with the quantum well structure showing the negative differential resistance (NDR), it is essential to increase both the peak-to-valley current ratio (PVCR) and the peak current density ($J_p$) for the accurate switching operation and the high output of the device. In this work, a resonant interband tunneling diode (RITD) with single quantum well structure, which is composed of $In_{0.53}Ga_{0.47}As/ln_{0.52}Al_{0.48}As$ heterojunction on the InP substrate, is suggested to improve the PVCR and $J_p$ through the narrowed tunnel barriers. As the result, the measured I-V curves showed the PVCR over 60.

• 전자공학회논문지D
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• 제34D권4호
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• pp.27-32
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• 1997

In resonant tunneling diodes with the quantum well structure showing the negative differential resistance (NDR), it is essential to increase both the peak-to-valley current ratio (PVCR) and the peak current desnity ( $J_{p}$) for the accurate digital switching operation and the high output of the device. In this work, a resonant interband tunneling diode (RITD) with single quantum well structure, which is composed of I $n_{0.47}$As/I $n_{0.52}$A $l_{0.48}$As heterojunction on the InP substrate, is fabricated ot improve PVCR and JP, and then the dependence of I-V charcteristics on the width of the quantum well was investigated.d.ted.d.

• 전자공학회논문지A
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• 제31A권2호
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• pp.75-80
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• 1994

AlAs/GaAs/AlAs RTDs(Resonant Tunneling Diodes) are fabricated and current-voltage properties of them are measured. At room temperature, peak to valley ratio is 2.4 NOT.AND.OR logic gates and Flip-Flop are fabricated using the bistable characteristics of RTDs. Although NOT.AND.OR logic gates need 5~8 transistors. only one RTD is sufficient to fabricate the logic gates. Since the switching time is very short(<10$^12$sec), it is possible to drive the semiconductor circuits fast and integrate them very large. And it is convinced the possibility of integrating RTDs to multilevel logic circuits by observing two peaks of similar current in the serial connection of two RTDs.

• Journal of Power Electronics
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• 제16권1호
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• pp.227-237
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• 2016

A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.