• Proceedings of the Korean Magnestics Society Conference
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• 2003.06a
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• pp.60-61
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• 2003

Theoretical considerations on a giant magneto-impedance (GMI) effect in amorphous ribbons (i.e., thin films) have been made in terms of the expressions of effective permeability and impedance derived in the frame of classical electrodynamics and ferromagnetism. The dependence of GMI effect on the external do magnetic field (H$\_$ext/) and the frequency of alternating current are simulated and discussed in the knowledge of energy conversion consisting of the current energy loss, the ferromagnetic energy consumption, and the magnetic energy storage in the film. The obtained results are summarized as follow: (a) As frequency f< 20 ㎒, the real part of effective permeability (${\mu}$′) changes slightly. The peak of the ${\mu}$′curve always locates at H$\_$ext/=H$\_$ani/ - the anisotropy field. However, the peak value of ${\mu}$′ tends to increase with increasing frequency in the frequency range of 11-20 ㎒. (b) In the frequency range, f= 21-23 ㎒, a negative peak additionally appears. Meanwhile, both the positive and negative peak values rapidly increase with increasing frequency and their peak positions shift towards a high H$\_$ext/. (c) The positive peak value of ${\mu}$′ starts to decrease at f= 29 ㎒ and its negative peak does so at about 35 ㎒. Then, both peaks keep such a tendency and their peak positions move to high H$\_$ext/, as increasing frequency. (d) The dependence of the imaginary part of effective permeability (${\mu}$") on the external dc magnetic field and the frequency of the alternating field indicates that there is only one peak involved in ${\mu}$" for the whole frequency range. (e) The impedance vs. magnetic field curves at various frequencies show that there is a critical value of frequency around f= 18-19 ㎒ where the transition between two frequency regimes occurs; the one (low frequency) in which ${\mu}$′ predominantly contributes to the GMI effect and the other (high frequency) in which ${\mu}$" determines the GMI effect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.98-104
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• 2006

The conventional burst-mode APC(Automatic Power Control) circuit had an effective structure that was suitable for a low power consumption and a monolithic chip. However, as data rate was increased, it caused errors due to the effect of the zero density. In this paper, we invented a new structured peak-comparator which could compensate the unbalance of the injected currents using double gated MOS and MOS diode. And we proposed a new burst-mode APC adopting it. The new peak-comparator in the proposed APC was very robust to zero density variations maintaining the correct decision point of the current comparison at high data rate. It was also suitable for a low power consumption and a monolithic chip due to lack of large capacitors.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1480-1488
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• 2015

In this paper, a revolutionary buck converter is proposed with soft-switching technology, which is realized by a coupled inductor. Both zero-voltage switching (ZVS) of main switch and zero-current switching (ZCS) of freewheeling diode are achieved at turn on and turn off without using any auxiliary circuits by the resonance between the parasitic capacitor and the coupled inductor. Furthermore, the peak voltages of the main switch and the peak current of the freewheeling diode are significantly reduced by the coupled inductor. As a result, the proposed converter has the advantages of simple circuit, convenient control, low consumption and so on. The detailed operation principles and steady-state analysis of the proposed ZVS-ZCS buck converter are presented, and detailed power loss analysis and some simulation results are also included. Finally, experimental results based on a 200-W prototype are provided to verify the theory and design of the proposed converter.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.388-394
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• 2015

The inrush current of a large inductive load can be reduced with a soft starter; however, the large inrush current caused by simultaneous bulk starts (SBSs) cannot be effectively reduced. In order to reduce the high inrush current and voltage sag owing to the SBSs of large capacity inductive loads within a power network, a novel hybrid sequential start control system is proposed, implemented on embedded systems, and evaluated with a testbed in this study. From the experimental and simulation results of the proposed control system, the inrush current could be effectively restricted below the maximum current capacity of a power distributing board. Moreover, with the proposed system, power cost typically dictated by the peak power consumption can be fairly reduced, and the quality of the power system connected to the inductive loads can be efficiently increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.28-36
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• 2008

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.304-309
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• 2005

This paper presents an electronic ballast using a step down converter, a low frequency inverter for high intensity short-arc discharge lamp. The proposed ballast is composed of a full-wave rectifier, a step down converter operated as a current source with power regulation and a low frequency inverter with external ignition circuit. The ignition circuit generates high voltage pulse of $3{\sim}5[kV]$ peak, 130[Hz] periodically. Moreover, it is able to reignite at regular intervals by protective circuit. As experimental results on the test, acoustic resonance phenomenon is eliminated by operating the low frequency square wave voltage and current. Lamp voltage, current and consumption power are measured 123.8[V], 8.1[A] and 1,002[W], respectively. It was confirmed that the designed ballast operate the lamp with a constant power.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.10
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• pp.14-20
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• 2009

It is very important for power stability to suppress the excessive fault current happened frequently in the real power grid The superconducting fault current limiter (SFCL) is one of the most effective ways to reduce the fault current among the facilities developed so far. In this paper, we have investigated the operating characteristics of the power grid with the SFCL according to three types such as the single, double and triple line-to-ground faults. In addition, we analyzed the consumption power of the superconducting units based on the working data of the SFCL. We confirmed that the fault current could be limited lower than its peak value to 85 percentage in initial fault condition and to 85 percentage after one cycle in the matrix-type SFCL. The consumption powers of the superconducting units were almost equal by reduction of the difference of the critical current between superconducting units element.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.333-338
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• 2008

In this paper, a new NMOS current-mirror type bridge rectifier for driving RFID chips, whose minimum input voltage required to obtain the effective DC output voltage is low enough and whose power dissipation can be reduced than that of conventional one, is proposed. The designed rectifier is able to supply high enough and well-rectified DC voltages to drive RFID transponder chips for the frequency range of 13.56 MHz HF(for ISO 18000-3), 915 MHz UHF(fur ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Output characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit. And the circuitry method for effective reducing of the gate leakage current due to the increasing of operating frequency is also proposed theoretically. Using this method, the power consumption of $100\;{\mu}W$ and the DC output voltage of 2.13V for 3V peak-to-peak input voltage and $45\;K{\Omega}$ load resistance are obtained. Compared to conventional one, the proposed rectifier operates in more stable and shows superior characteristics in UHF and microwave frequencies.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.309-314
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• 2014

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.