• Journal of the Korean Society for Precision Engineering
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• v.30 no.9
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• pp.1001-1006
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• 2013

Projection-based stereolithography is divided into constrained-surface and free-surface type according to controlling liquid layer. The constrained-surface type has a uniform layer thickness due to the use of a projection window, which covers the pattern generator such as liquid crystal display. However, the adhered resin on the projection window causes trouble and requires great separation force when the cured layer is separated from the window. To minimize the separation force, we developed a system to measure the separation force. The influence of material covering the pattern generator and the resin temperature is investigated in the system. Several structures according to the resin temperature and the velocity of z-axis elevation are compared. As a result, the fabrication condition to minimize the separation force reduces the process time.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.33 no.7
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• pp.541-551
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• 2009

Configuration of the inlet transition square duct (hereinafter referred to as "transition duct") for heat recovery steam generator (hereinafter referred to as "HRSG") in combined cycle power plant is limited by the construction type of HRSG and plant site condition. The main purpose of the present study is to analyze the effect of a variation in turbulent flow pattern by roof slop angle change of transition duct for horizontal HRSG, which is influencing heat flux in heat transfer structure to the finned tube bank. In this study, a computational fluid dynamics(CFD) is applied to predict turbulent flow pattern and comparisons are made to 1/12th scale cold model test data for verification. Re-normalization group theory (RNG) based k-$\epsilon$ turbulent model, which improves the accuracy for rapidly strained flow and swirling flow in comparison with standard k-$\epsilon$ model, is used for the results cited in this study. To reduce the amount of computer resources required for modeling the finned tube bank, a porous media model is used.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.878-881
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• 2005

A Stereolithography technology is based on stacking of sliced layer from STL file that is converted from 3-dimensional CAD data. A microstereolithography technology is evolved from conventional stereolithography to fabricate microstructures. In this technology, we have to consider influence of resin flow to make refresh surface. To generate new resin surface, stage has to be moved downward deeply and upward to desired position. At this time, resin flow affects to refresh surface of resin. And resin viscosity is the key factor in simulation of resin flow. By setting optimal refresh time for resin surface, total fabrication time is reduced and there is no damage to fabricated layers. In this research, we simulate resin flow using CFD software and derive optimal stage moving time and dwelling time.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.4
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• pp.134-139
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• 2008

A spirally arrayed nano-pattern is designed as a model pattern for the next generation optical storage media. The pattern consists off types of embossed rectangular dot, which are 50nm, 100nm, 150nm and 200nm in length and 50nm in width. The height of the dot is designed to be 50nm. The pitch of the spiral track of the pattern is 100nm. A ER(Electron resist) master for this pattern is fabricated by e-beam lithography process. The ER is first spin-coated to be 50nm thick on a Si wafer and then the model pattern is written on the coated ER layer by e-beam. After developing this pattern written wafer in the solution, a ER pattern master is fabricated. The most conventional e-beam machine can write patterns in orthogonal way, so we made our own pattern generator which can write the pattern in circular or spiral way. This program generates the patterns to be compatible with the e-beam machine from Raith(Raith 150). To fabricate 50nm pattern master precisely, a series of experiments were done including the design compensation for the pattern size, optimization of the dose, acceleration voltage, aperture size and developing. Through these experiments, we conclude that the higher accelerating voltages and smaller aperture size are better for mastering the nano pattern which is in order of 50nm. With the optimized e-beam lithography process, a spiral arrayed 50nm pattern master adopting PMMA resist was fabricated to have dimensional accuracy over 95% compared to the designed. Using this pattern master, a metal pattern stamp will be fabricated by Ni electro plating for injection molding of the patterned plastic substrate.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.11 no.4
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• pp.331-338
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• 2017

In this study, a portable x-ray generator was manufactured and a real-time image acquisition system was constructed using the image intensifier from the generated generator. We have developed a real - time position error verification system that can verify whether the artificial joint position is different from the initial image from the acquired image. The template image of the region of interest is extracted from the reference image using the pattern matching technique and compared with the image to be compared. As a result, It is shown that real - time position error verification is achieved by displaying the difference angle. This system is portable type, has a self-shielding facility, and the output of the irradiation device can be manufactured in a small size of 1kw and can be used as a portable type. In case of emergency patients in the non-destructive field for industrial use, It has proved effective for use in small areas such as feet.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1B
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• pp.47-55
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• 2009

In recent network intrusion detection systems, regular expressions are used to represent malicious packets. In order to process incoming packets through high speed networks in real time, we should perform hardware-based pattern matching using the configurable device such as FPGAs. However, operating speed of FPGAs is slower than giga-bit speed network and so, multi-byte processing per clock cycle may be needed. In this paper, we propose a hardware architecture of multi-byte based regular expression pattern matching and implement the pattern matching circuit generator. The throughput improvements in four-byte based pattern matching circuit synthesized in FPGA for several Snort rules are $2.62{\sim}3.4$ times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.2
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• pp.156-163
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• 2013

The use of an error-correcting code is essential in communication systems where the channel is noisy. When channel coding parameters are unknown at a receiver side, decoding becomes difficult. To perform decoding without the channel coding information, we should estimate the parameters. In this paper, we introduce a method to reconstruct the generator polynomial of BCH(Bose-Chaudhuri-Hocquenghem) codes based on the idea that the generator polynomial is compose of minimal polynomials and BCH code is cyclic code. We present a probability compensation method to improve the reconstruction performance. This is based on the concept that a random data pattern can also be divisible by a minimal polynomial of the generator polynomial. And we confirm the performance improvement through an intensive computer simulation.

• Journal of Korea Multimedia Society
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• v.8 no.11
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• pp.1556-1564
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• 2005

Various optimization techniques are deployed in the compilation process of a source program for improving the program's execution speed and reducing the size of the source code. Of the optimization pattern matching techniques, the string pattern matching technique involves finding an optimal pattern that corresponds to the intermediate code. However, it is deemed inefficient due to excessive time required for optimized pattern search. The tree matching pattern technique can result in many redundant comparisons for pattern determination, and there is also the disadvantage of high cost involved in constructing a code tree. The objective of this paper is to propose a table-driven code optimizer using the DFA(Deterministic Finite Automata) optimization table to overcome the shortcomings of existing optimization techniques. Unlike other techniques, this is an efficient method of implementing an optimizer that is constructed with the deterministic automata, which determines the final pattern, refuting the pattern selection cost and expediting the pattern search process.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.4
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• pp.779-787
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• 2010

In this paper, We introduce electrical tracking generated from surface activity associated with flow of leakage current on insulator under wet and contaminated conditions and design electrical tracking pattern recognition system by using LabVIEW. We measure the leaking current of contaminated wire by using LabVIEW software and the NI-c-DAQ 9172 and NI-9239 hardware. As pattern recognition algorithm and optimization algorithm for electrical tracking system, neural networks, Radial Basis Function Neural Networks(RBFNNs) and particle swarm optimization are exploited. The designed electrical tracking recognition system consists of two parts such as the hardware part of electrical tracking generator, the NI-c-DAQ 9172 and NI-9239 hardware and the software part of LabVIEW block diagram, LabVIEW front panel and pattern recognition-related application software. The electrical tracking system decides whether electrical tracking generate or not on electrical wire.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.