• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1344-1348
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• 1999

This paper proposes concurrent event propagation technique for timing analysis. The technique makes it possible to find several input vectors and sensitizable paths at the same time. The concurrent event propagation technique is based on the event driven simulation and the timing analysis technique with boolean equations. The technique propagates as many events as possible at the same time while preventing propagation of boolean terms which do not sensitize paths. Since events do not propagate through false paths, the longest path which successfully propagates events to one of the primary outputs is one of the longest sensitizable paths. The technique can speed up timing analysis by unifying path sensitization and maximum delay calculation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.1-9
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• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1346-1353
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• 1996

In this paper, we propose a modeling method for the flip-flops and test generation algorithms to detect the faults in the sequential circuits using VHDL in the high-level design environment. RS, JK, D and T flip-flops are modeled using data flow types. The sequence of micro-operation which is the basic structure of a chip-level leads to a control point where varnishing occurs to one of two micro- operation sequence. In order to model the fault of one micro-operation(FMOP) that perturb another micro-operation effectively, the concept of goal trees and some heuristic rules are used. Given a faulty FMOP or fault of control point (FCON), a test pattern is generated by fault sensitization, path sensitization and determination of the imput combinations that will justify the path sensitization. The fault models are restricted to the data flow model in the ARCHITECTURE statement of VHDL. The proposed algorithm is implemented in the C language and its efficiency is confirmed by some examples.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.1-10
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• 1998

This paper is to propose an algorithm named as DYSAC to find the critical path(the longest sensitizable path) in a large digital circuit, whose purpose is to reduce the time to find critical path and to find critical paths of the circuits for which the previous methods could not find one. Also a set of path sensitization criteria named as DYPSEC is proposed, which is used to select a path from input to the output inside the DYSAC. The DYSAC consists of two sub-algorithms; the level assignment algorithm to assign a level to each node and the critical path selection algorithm to select the sensitizable path. The proposed algorithm was implemented with C-language on SUN Sparc and applied to the ISCAS'85 benchmark circuits to make sure if it works correctly and finds the correct critical path. Also, the results from the experiments were compared to the results from the previous works. The comparison items were the ability to find the critical path and the speed, in both of which the proposed algorithm in this paper shows better results than others.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.9
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• pp.745-752
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• 1990

This paper deals with the path sensitization algrithm from PI to PO center on the nodes of high testability mainstay when CUT is tested by pseudo exhaustive testing. In CUT, the node definition of high testability mainstay treats the testability values of the entire nodes with the population composed of the raw data, and after we examined the level of significance(1-a) region, we accomplished in the estimation of the confidence interval of the testability. Focusing on the defined nodes of high testability mainstay, we performed the singular cover and consistency operation to the forward and backward logic gates. Thus, we easily generated the pseudo exhausitve test patterns. As a result, (1-a) region has 0.1579 and the pseudo exhaustive test patterns are least generated and the rate of test pattern is 1.22%, compared with exhaustive testing. (1-a) region has 0.2368 and this results exhibits the optimal performance of the singular cover and consistency operation. Applying the generated pseudo exhaustive test patterns to the stuck-at faults existing on the inputs and internal nodes in CUT, we verified this performance on the output. Thus, it is confirmed that functional testing of the proposed path sensitization algorithm is very useful.