• Journal of KIISE:Information Networking
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• v.31 no.1
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• pp.1-10
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• 2004

This study discusses Application-layer FEC using erasure codes. Because of the simple decoding process, erasure codes are used effectively in Application-layer FEC to deal with Packet-level errors. The large number of parity packets makes the loss rate to be small, but causes the network congestion to be worse. Thus, a redundancy control algorithm that can adjust the number of parity packets depending on network conditions is necessary. In addition, it is natural that high-priority frames such as I frames should produce more parity packets than low-priority frames such as P and B frames. In this paper, we propose a redundancy control algorithm that can adjust the amount of redundancy depending on the network conditions and depending on data priority, and test the performance in simple links and congestion links.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.571-577
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• 2009

This paper proposes some new improved versions of node-wise VCRBP algorithm for low-density parity-check (LDPC) codes, called forced-convergence node-wise VCRBP algorithm and sign based node-wise VCRBP, both of which significantly reduce the decoding complexity and latency, with only negligible deterioration in error correcting performance.

• ETRI Journal
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• v.36 no.1
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• pp.171-174
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• 2014

In weighted bit-flipping-based algorithms for low-density parity-check (LDPC) codes, due to the existence of overconfident incorrectly received bits, the metric values of the corresponding bits will always be wrong in the decoding process. Since these bits cannot be flipped, decoding failure results. To solve this problem, an improved parallel weighted bit flipping algorithm is proposed. Specifically, a reliability-saturation strategy is adopted to increase the flipping probability of the overconfident incorrectly received bits. Simulation results show that the error floor of LDPC codes is greatly lowered.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.841-847
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• 2009

In this paper we propose a high-performance Hybrid ARQ scheme employing Chase combining based on LDPC (Low-Density Parity-Check) codes. The proposed scheme uses symbol mapping diversity and turbo demodulation to improve decoding performance. We analyze the performance of the proposed scheme by EXIT (EXtrinsic Information Transfer) chart and compare its performance with several symbol mappings.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.991-996
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• 2008

In this paper, we propose an LDPC-coded hybrid ARQ system using incremental redundancy and retransmission of a part of the transmitted packets. We also present a simple criterion for choosing two methods to support a desired throughput efficiently. Furthermore, we show that the throughput performance can be improved when multi-edge type LDPC codes with the structure of Raptor codes are employed for a hybrid ARQ scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.3-10
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• 2015

Application of polar codes to rate-adaptive asymmetric Slepian-Wolf coding is considered. We propose a method of constructing polar codes which supports rate adaptivity. The proposed polar distributed source coding with successive cancellation list decoding performs closer to the Slepian-Wolf bound than the low density parity check accumulate (LDPCA) codes in the same framework.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.29-36
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• 2020

Wear-leveling techniques and Error Correction Codes (ECCs) are essential for the improvement of the reliability and durability of flash memories. Low-Density Parity-Check (LDPC) codes have higher error correction capabilities than conventional ECCs and have been applied to various flash memory-based storage devices. Conventional wear-leveling schemes using only the number of Program/Erase (P/E) cycles are not enough to reflect the actual aging differences of flash memory components. This paper introduces an actual aging measurement scheme for flash memory wear-leveling using LDPC decoding information. Our analysis, using error-rates obtained from an flash memory module, shows that LDPC decoding information can represent the aging degree of each block. We also show the effectiveness of the wear-leveling based on the proposed scheme through wear-leveling simulation experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.8
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• pp.662-668
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• 2013

Mobile communication systems have been adopting link adaptive transmission schemes such as adaptive modulation and coding (AMC) and hybrid-ARQ (HARQ). Incremental redundancy (IR) HARQ scheme is known to be highly efficient in terms of throughput and power consumption and can be a good solution for mobile communication systems. In this paper, we propose an IR-HARQ scheme based on dual-diagonal parity-type block LDPC codes in which we define a transmission priority of coded bits and propose the sub-packet construction rule. We present the throughput performance of IR-HARQ with various modulation and coding and multi-antenna modes. Consequently, the proposed scheme provides the improvement of system throughput by elaborate link adaptation with CQI information.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1654-1665
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• 2008

This paper presents bit splitting methods to apply multilevel modulation to iterative codes such as turbo code, low density parity check code and turbo product code. Log-likelihood ratio method splits multilevel symbols to soft decision symbols using the received in-phase and quadrature component based on Gaussian approximation. However it is too complicate to calculate and to implement hardware due to exponential and logarithm calculation. Therefore this paper presents Euclidean, MAX, sector and center focusing method to reduce the high complexity of LLR method. Also, this paper proposes optimal soft symbol split method for three kind of iterative codes. Futhermore, 16-APSK modulator method with double ring structure for applying DVB-S2 system and 16-QAM modulator method with lattice structure for T-DMB system are also analyzed.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1026-1035
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• 2011

This paper presents generalization and application for the conventional SISO decoding algorithm of Block Turbo Codes. R. M. Pyndiah suggested an iterative SISO decoding algorithm for Product Codes, two-dimensionally combined linear block codes, on AWGN channel. It wascalled Block Turbo Codes. Based on decision of Chase algorithm which is SIHO decoding method, SISO decoder for BTC computes soft decision information and transfers the information to next decoder for iterative decoding. Block Turbo Codes show Shannon limit approaching performance with a little iteration at high code rate on AWGN channel. In this paper we generalize the conventional decoding algorithm of Block Turbo Codes, under BPSK modulation and AWGN channel transmission assumption, to the LLR value based algorithm and suggest an application example such as concatenated structure of LDPC codes and Block Turbo Codes.