• Journal of the Korean Society for Railway
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• v.8 no.1
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• pp.1-5
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• 2005

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15％ In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• Tribology and Lubricants
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• v.15 no.1
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• pp.24-28
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• 1999

This paper describes a new pivoting technique to improve bearing performance in pivoted pad thrust bearings. This new technique adjusts the pivot line in a line pivoted pad thrust bearing to be parallel to the trailing edge of a sector shaped pad. Bearing performance factors such as load carrying capacity, frictional torque and flow rate are numerically investigated for conventional point-pivoted and line-pivoted pads and for the new parallel-line pivoting technique. It is shown that the load carving capacity can be maximized with the new technique.

• Journal of the Korean Solar Energy Society
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• v.35 no.6
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• pp.9-15
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• 2015

In this paper, a parallel operating technique for the stand alone photovoltaic (PV) power conditioning system (PCS) is proposed. The proposed parallel operating technique can increase the power rating of the system easily. Also, it provide three-phase connection function. The proposed technique does not separated master and slave system. Also, it does not use the separated synchronization line. Therefore, the PCS can supply continuous power even if one of the PCS breaks down. This technique is composed of a phase locked loop (PLL) control, droop control, current limit control and etc. Experimental result obtained on 2-kW prototype to verify the proposed technique.

• Journal of Korea Multimedia Society
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• v.21 no.11
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• pp.1254-1262
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• 2018

Many parallel lines may be shown in our real life and they are useful for analyzing structure of objects or buildings. In this paper, a vision based technique for estimating three-dimensional direction of parallel lines is suggested, which uses a calibrated camera and is applicable to an image being captured from the camera. Correctness of the technique is theoretically described and discussed in this paper. The technique is well applicable to measurement of orientation of a pallet in a warehouse, because a pair of parallel lines is well detected in the front plane of the pallet. Thereby the technique enables a forklift with a well-calibrated camera to engage the pallet automatically. Such a forklift in a warehouse can engage a pallet on a storing rack as well as one on the ground. Usefulness of the suggested technique for other applications is also discussed. We conducted an experiment of measuring a real commercial pallet with various orientation and distance and found for the technique to work correctly and accurately.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1235-1240
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• 2004

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit had been successfully applied to the inductively coupled passive RFID system working at a frequency of 13.56MHz in order to process the detection of logical faults more fast and the system had been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates in the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• Journal of Korea Multimedia Society
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• v.23 no.10
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• pp.1229-1235
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• 2020

A line parallel to the ground is frequently shown in our daily life, which enables us to guess its direction. Especially, such a guess tends to become clear when a vanishing line of the ground is shown together. In this paper, a vision based pallet measurement method is suggested, which uses a technique for estimating three-dimensional direction of a line parallel to the ground. The technique computes actually a vector heading to intersection of a given imaged line parallel to the ground and the ground vanishing line determined previously on calibrating a measurement camera. Through an experiment of measuring a real commercial pallet with various orientation and distance, we found that the technique could measure the orientation of the pallet correctly and accurately. The technique worked well even though an edge line available on the front plane of a pallet was almost parallel to the ground vanishing line.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.3
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• pp.599-604
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• 2017

Nowadays reactance method is being used as a technique for fault location in parallel feeding AC traction power system. However, implementation of this method requires a large number of field tests(ground fault) which is a huge burden on the operators. This paper presents a new estimation technique using quadratic interpolation to reduce number of times for field test and improves the accuracy of fault location. To verify a new technique, we solve AT feeding circuit and model it using PSCAD/EMTDC. Finally this paper conducts a comparative analysis of usefulness between a new technique and real field data.

• Journal of Power Electronics
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• v.12 no.6
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• pp.851-858
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• 2012

This paper presents resonant inverter tuning for current source parallel resonant induction heating systems based on a new self oscillating switching technique. The phase error is suppressed in a wide range of operating frequencies in comparison with Phase Locked Loop (PLL) techniques. The proposed switching method has the capability of tuning under fast changes in the resonant frequency. According to this switching method, a multi-frequency induction heating (IH) system is proposed by using a single inverter. In comparison with multi-level inverter based IH systems, the advantages of this technique are its simple structure, better transients and wide range of operating frequencies. A laboratory prototype was built with an operating frequency of 35 kHz to 55 kHz and 300 W of output power. The performance of the IH system shows the validity of the new switching technique.