• Journal of the Korean Mathematical Society
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• v.52 no.2
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• pp.373-388
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• 2015

In this paper, a novel parallel hybrid iterative method is proposed for finding a common element of the set of solutions of a system of equilibrium problems, the set of solutions of variational inequalities for inverse strongly monotone mappings and the set of fixed points of a finite family of nonexpansive mappings in Hilbert space. Strong convergence theorem is proved for the sequence generated by the scheme. Finally, a parallel iterative algorithm for two finite families of variational inequalities and nonexpansive mappings is established.

• Proceedings of the KSME Conference
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• 2008.11b
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• pp.2558-2561
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• 2008

In the present study, a parallel Taylor-Galerkin/level set based two-phase flow code was developed using finite element discretization and domain decomposition method based on MPI (Message Passing Interface). The proposed method can be utilized for the analysis of a large scale free surface problem in a complex geometry due to the feature of FEM and domain decomposition method. Four-step fractional step method was used for the solution of the incompressible Navier-Stokes equations and Taylor-Galerkin method was adopted for the discretization of hyperbolic type redistancing and advection equations. A Parallel ILU(0) type preconditioner was chosen to accelerate the convergence of a conjugate gradient type iterative solvers. From the present parallel numerical experiments, it has been shown that the proposed method is applicable to the simulation of large scale free surface flows.

• Journal of applied mathematics & informatics
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• v.19 no.1_2
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• pp.77-92
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• 2005

An efficient parallel algorithm is presented to find a maximum weight independent set of a permutation graph which takes O(log n) time using O($n^2$/ log n) processors on an EREW PRAM, provided the graph has at most O(n) maximal independent sets. The best known parallel algorithm takes O($log^2n$) time and O($n^3/log\;n$) processors on a CREW PRAM.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1575-1579
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• 1999

Embedded processors often accommodate two instruction sets, a standard instruction set and a compressed instruction set. With the compressed instruction set, code size can be reduced while instruction count (and consequently execution time) can be increased. To achieve code size reduction without significant increase of execution time, this paper proposes a new compressed instruction set architecture, called TOE (Two Operations Execution). The proposed instruction set format includes the parallel bit that indicates an instruction can be executed simultaneously with the next instruction. To add the parallel bit, TOE instruction format reduces the destination register field. The reduction of the register field limits the number of registers that are accessible by an instruction. To overcome the limited accessibility of registers, TOE adapts non-homogeneous register partition in which registers are divided into multiple subsets, each of which are accessed by different groups of instructions. With non-homogeneous registers, each instruction can access only a limited number of registers, but an entire program can access all available registers. With efficient non-homogeneous register allocator, all registers can be used in a balanced manner. As a result, the increase of code size due to register spills is negligible. Experimental results show that more than 30% of TOE instructions can be executed in parallel without significant increase of code size when compared to existing Thumb instruction set.

• Journal of Power Electronics
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• v.14 no.1
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• pp.22-29
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• 2014

Current sharing between modules in a converter parallel operation is very important for the reliability of the system. This paper proposes an improved droop method that can effectively improve current sharing accuracy. The proposed method adaptively adjusts the output voltage set-point of each module according to the current set-points. Unlike conventional droop control, modules share a signal line to communicate with each other. Nevertheless, since signals are simple and in digital form, the complexity of the circuitry is much less and noise immunity is much better than those of conventional methods utilizing communication. The operation principle and design procedure of the proposed method are described in detail. Results of the experiment on two boost converters operating in parallel under the specification of a TFT LCD TV panel power supply verify the validity of the proposed scheme.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.32 no.2
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• pp.125-132
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• 2008

The bubble dynamics and heat transfer associated with nucleate boiling in parallel microchannels is studied numerically by solving the equations governing conservation of mass, momentum and energy in the liquid and vapor phases. The liquid-vapor interface is tracked by a level set method which is modified to include the effects of phase change at the interface and contact angle at the wall. Also, the reversible flow observed during flow boiling in parallel microchannels has been investigated. Based on the numerical results, the effects of contact angle, wall superheat and the number of channels on the bubble growth and reversible flow are quantified.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1680-1686
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• 1996

The deterministic update method of intensional predicates in a parallel deductive database that deductive database is distributed in a parallel computer architecture in needed. Using updated data from the deterministic update method, a strategy for parallel evaluation of intensional predicates is required. The paper is concerned with an approach to updating parallel deductive database in which very insertion or deletion can be performed in a deterministic way, and an extended parallel semi-naive evaluation algorithm in a parallel computer architecture. After presenting an approach to updating intensional predicates and strategy for parallel evaluation, its implementation is discussed. A parallel deductive database consists of the set of facts being the extensional database and the set of rules being the intensional database. We assume that these sets are distributed in each processor, research how to update intensional predicates and evaluate using the update method. The parallel architecture for the deductive database consists of a set of processors and a message passing network to interconnect these processors.

• Journal of the Korean Statistical Society
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• v.13 no.2
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• pp.114-120
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• 1984

A parallel flats fraction for the $3^n$ design is defined as union of flats ${t}At=c_i(mod 3)}, i=1,2,\cdots, f$ and is symbolically written as At=C where A is rank r. The A matrix partitions the effects into n+1 alias sets where $u=(3^{n-r}-1)/2. For each alias set the f flats produce an ACPM from which a detection matrix is constructed. The set of all possible parallel flats fraction C can be partitioned into equivalence classes. In this paper, we develop some properties of a detection matrix and C.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.151-156
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• 2012

The current study presents a zero-one integer programming approach to determine the minimum break point set for the coordination of directional relays. First, the network is reduced if there are any parallel lines or three-end nodes. Second, all the directed loops are enumerated to reduce the iteration. Finally, the problem is formulated as a set-covering problem, and the break point set is determined using the zero-one integer programming technique. Arbitrary starting relay locations and the arbitrary consideration of relay sequence to set and coordinate relays result in navigating the loops many times and futile attempts to achieve system-wide relay coordination. These algorithms are compared with the existing methods, and the results are presented. The problem is formulated as a setcovering problem solved by the zero-one integer programming approach using LINGO 12, an optimization modeling software.