• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.5
• /
• pp.71-80
• /
• 1995

The usual approach for desinging a fast multiplier involves finding a way to quickly add up all the partial products, based on parital product recoding scheme and carry-save addition. This paper describes theoretical medels for area and time complexities of Multibit Reconding Paralle Multiplier (MRPM), which is a generalization of the modified Booth recoding scheme. Based on the proposed models, time performance, hardware requirements and area-time efficiency are analyzed in order to determine optimal recoding size for very large scale integration (VLSI) realization of the MRPM. Some simulation results show that the MRPM with large multiplier and multiplicand size has optimal area-time efficiency at the recoding size of 4-bit.

• Proceedings of the IEEK Conference
• /
• 2002.06e
• /
• pp.79-82
• /
• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials in existence coefficients over finite field GF(3$^{m}$ ). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of (m+1)$^2$identical cells, each cell consists of single mod(3) additional gate and single mod(3) multiplicative gate. Proposed multiplier need single mod(3) multiplicative gate delay time and m mod(3) additional gate delay time not clock. Also, the proposed architecture is simple, regular and has the property of modularity, therefore well-suited for VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.3B
• /
• pp.355-361
• /
• 2001

유한체(Galois Field) 상에서의 곱셈(multiplication)을 구현하는 방법은 크게 병렬 곱셈기(parallel multiplier)와 직렬 곱셈기(serial multiplier)로 나누어질 수 있는데, 구현시 하드웨어 면적을 작게 차지한다는 장점 때문에 직렬 곱셈기가 널리 사용된다. 하지만 이 직렬 곱셈기를 이용하여 계산을 하기 위해서는 병렬 곱셈기에 비해 많은 시간이 필요하게 된다. 직렬기법과 병렬기법의 결합이 이를 보완할 수 있게 된다. 본 논문에서는 복잡도는 직렬 곱셈기와 큰 차이가 없으면서 연산시간을 줄인 곱셈기*(multiplier)를 제안하였다. 이 곱셈기를 사용하면 복잡도는 크게 늘어나지 않았으면서 유한체 상에서의 곱셈을 하는데 필요한 시간을 줄이는 효과를 얻을 수 있다.

• Journal of the Semiconductor & Display Technology
• /
• v.20 no.2
• /
• pp.29-33
• /
• 2021

A 5.8-GHz 1W wireless power transmission system was used for charging a smart phone. The voltage of one RF power receiver with antenna was not enough for charging. Several power receivers for charging a smart phone was connected serially. The voltage of several RF power receivers are highly enough for charging a smart phone within 50cm. However, the lack of current from small capacitances of RF-DC converters is not suitable for charging smart phone. It means very long charging time. In this paper, the voltage multiplier circuits for RF-DC converters were analyzed to increase the current and voltage at the same time to reduce the charging time in smartphone RF wireless charging. Through the analysis of multiplier circuits, the 7-stage parallel multiplier circuit with voltage-doubler units are suitable for charging the smartphone, which supplies 5V and 700mA at 3V@5.8GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.104-112
• /
• 2007

We developed a $7{\times}7$ parallel multiplier using LTPS-TFT. The proposed multiplier has multi-valued logic 7-3 Compressor with folding, 3-2 Compressor, and final carry propagation adder. Architecture minimized the carry propagation. And power consumption reduced by switching the current source to the circuit which is operated in current mode. The proposed multiplier improved PDP by 23%, EDP by 59%, and propagation delay time by 47% compared with Wallace Tree multiplier.

• Journal of IKEEE
• /
• v.12 no.4
• /
• pp.211-216
• /
• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.7
• /
• pp.1-8
• /
• 2008

Low Density Parity Check codes(LDPC) are recently focused on communication systems due to its good performance. The standard of WiBro has also included LDPC codes as a channel coding. The weak point of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which limit throughput. In this paper, we propose semi-parallel architecture by using cyclic shift registers and exclusive-OR without conventional Matrix Vector Multipliers over the standard parity check matrices with Circulant Permutation Matrices(CPM). Furthermore, multi-rate encoder is designed by using proposed architecture. Our encoder with multi-rate for IEEE 802.16e LDPC has lower clock cycles and higher throughput.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.2
• /
• pp.323-329
• /
• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• Proceedings of the IEEK Conference
• /
• 2001.06e
• /
• pp.47-50
• /
• 2001

Nowadays ARM7 core is used in many fields such as PDA systems because of the low power and low cost. It is a general-purpose processor, designed for both efficient digital signal processing and controller operations. But the advent of the wireless communication creates a need for high computational performance for signal processing. And then This paper has been designed a floating-point multiplier compatible to IEEE-754 single precision format for ARMTTDMI performance improvement.

• Proceedings of the Korean Information Science Society Conference
• /
• 2003.04a
• /
• pp.272-274
• /
• 2003

유한체 GF(2$^{m}$ ) 상의 산술 연산 중 곱셈 연산의 효율적인 구현은 암호이론 분야의 어플리케이션에서 매우 중요하다. 본 논문에서는 All-One 다항식에 의해 정의된 GF(2$^{m}$ ) 상의 효율적인 Bit-Parallel 정규기저 곱셈기를 제안한다. 게이트 및 시간 면에서 본 논문의 곱셈기의 complexity는 이전에 제안된 같은 종류의 곱셈기 보다 낮거나 동일하다. 그리고 본 논문의 곱셈기는 이전 곱셈기 보다 더 모듈적이어서 VLSI 구현에 적합하다.