• Title/Summary/Keyword: parallel communication

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High-Performance Variable-Length Reed-Solomon Decoder Architecture for Gigabit WPAN Applications (기가비트 WPAN용 고성능 가변길이 리드-솔로몬 복호기 구조)

  • Choi, Chang-Seok;Lee, Han-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.1
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    • pp.25-34
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    • 2012
  • This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.

Study on High Speed Routers(I)-Labeling Algorithms for STC104 (고속라우터에 대한 고찰(I)-STC104의 레이블링 알고리즘)

  • Lee, Hyo-Jong
    • The KIPS Transactions:PartA
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    • v.8A no.2
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    • pp.147-156
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    • 2001
  • A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

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Refined fixed granularity algorithm on Networks of Workstations (NOW 환경에서 개선된 고정 분할 단위 알고리즘)

  • Gu, Bon-Geun
    • The KIPS Transactions:PartA
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    • v.8A no.2
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    • pp.117-124
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    • 2001
  • At NOW (Networks Of Workstations), the load sharing is very important role for improving the performance. The known load sharing strategy is fixed-granularity, variable-granularity and adaptive-granularity. The variable-granularity algorithm is sensitive to the various parameters. But Send algorithm, which implements the fixed-granularity strategy, is robust to task granularity. And the performance difference between Send and variable-granularity algorithm is not substantial. But, in Send algorithm, the computing time and the communication time are not overlapped. Therefore, long latency time at the network has influence on the execution time of the parallel program. In this paper, we propose the preSend algorithm. In the preSend algorithm, the master node can send the data to the slave nodes in advance without the waiting for partial results from the slaves. As the master node sent the next data to the slaves in advance, the slave nodes can process the data without the idle time. As stated above, the preSend algorithm can overlap the computing time and the communication time. Therefore we reduce the influence of the long latency time at the network and the execution time of the parallel program on the NOW. To compare the execution time of two algorithms, we use the $320{\times}320$ matrix multiplication. The comparison results of execution times show that the preSend algorithm has the shorter execution time than the Send algorithm.

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Horizontal Protocol Processing Architecture for High Performance Parallel Processing (고성능 병렬 처리를 위한 수평적인 프로토콜 처리 구조)

  • Kim, Pyeong-Jung;Park, Chi-Hang
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.6
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    • pp.1386-1396
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    • 1996
  • In the distributed multimedia application, high throughput and low delay is one of the most important QoS(Quality of Service) requirement. Emerging high speed communication offers transmission rate above Gbps, but it can not be utilized efficiently by the performance bottlenecks of communication protocols. To overcom the problem, we propose a horizontal processing architecture that processes data as soon as it arrive from the network. Unfortunately, the OSI protocol stack often imposes ordering constraints that prevent concurrent processing of the protocol layers. By using a fixed packet format, the network layer through the presentation layer are processed in parallel. Our prototype shows that the proposed model has performance improvement up to 61% more advantage than the conventional approach.

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Internet Based Remote Control and Monitoring System using Digital Timer (디지털 타이머를 이용한 인터넷 기반의 원격제어 및 모니터링)

  • Kim, E.J.;Kang, S.Y.;Bark, C.S.;Lim, Y.C.;Kim, G.W.
    • Proceedings of the KIEE Conference
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    • 2001.10a
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    • pp.245-248
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    • 2001
  • Recently, with the advancement of internet network the system has been needed to be controllable and observable through internet at industrial workplace. In this study, we developed the digital timer which has a communication function to control and observe many kinds of devices by combining relay and timer used for each type of control panel to realize control solution based on internet to be easily applicable at workplace with low cost and adding 485 serial communication module to have parallel expansibility and safety. And, this system was experimented and designed for easy system management and status check from remote station through internet. appling the developed digital timer to parallel sequence control of motor. As the result of experiment, the circuit configuration would be more simplified than the existing, and it is expected that multi-connection control and monitoring can be simply implemented with low cost equipment at industrial workplace.

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Comparison Speed of Pedestrian Detection with Parallel Processing Graphic Processor and General Purpose Processor (병렬처리 그래픽 프로세서와 범용 프로세서에서의 보행자 검출 처리 속도 비교)

  • Park, Jang-Sik
    • The Journal of the Korea institute of electronic communication sciences
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    • v.10 no.2
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    • pp.239-246
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    • 2015
  • Video based object detection is basic technology of implementing smart CCTV system. Various features and algorithms are developed to detect object, however computations of them increase with the performance. In this paper, performances of object detection algorithms with GPU and CPU are compared. Adaboost and SVM algorithm which are widely used to detect pedestrian detection are implemented with CPU and GPU, and speeds of detection processing are compared for the same video. As results of frame rate comparison of Adaboost and SVM algorithm, it is shown that the frame rate with GPU is faster than CPU.

A Study on Optimization of W-CDMA System Reverse Link Power Ratio using Multiple Access Interference Cancellation (역방향 채널 전력비에 따른 IMT-2000용 비동기 W-CDMA 시스템의 성능 분석)

  • 강명구;조장묵;진용옥
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.4 no.1
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    • pp.227-232
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    • 2000
  • This study applied asynchronous W-CDMA(3GPP) system that is suggested as an access method of IMT-2000, multimedia communication in next generation, and estimated fading channel by using pilot symbol different from traditional IS-95. And then, it applied PIC(Parallel Interference Cancellation) as multiple access interference cancellation and analyzed performance depending on the power rate between DPCCH(Control) and DPDCH(Data). As a result of simulation, it showed the best performance in C:D = 3:7 and 4:6, where set up as five users in case of hand design, and showed the best performance in C:D = 3:7, where did as ten users.

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Global Internet Computing Environment based on Java (자바를 기반으로 한 글로벌 인터넷 컴퓨팅 환경)

  • Kim, Hui-Cheol;Sin, Pil-Seop;Park, Yeong-Jin;Lee, Yong-Du
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.9
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    • pp.2320-2331
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    • 1999
  • Over the Internet, in order to utilize a collection of idle computers as a parallel computing platform, we propose a new scheme called GICE(Global Internet Computing Environment). GICE is motivated to obtain high programmability, efficient support for heterogeneous computing resources, system scalability, and finally high performance. The programming model of GICE is based on a single address space. GICE is featured with a Java based programming environment, a dynamic resource management scheme, and efficient parallel task scheduling and execution mechanisms. Based on a prototype implementation of GICE, we address the concept, feasibility, complexity and performance of Internet computing.

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Multiview Stereo Matching on Mobile Devices Using Parallel Processing on Embedded GPU (임베디드 GPU에서의 병렬처리를 이용한 모바일 기기에서의 다중뷰 스테레오 정합)

  • Jeon, Yun Bae;Park, In Kyu
    • Journal of Broadcast Engineering
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    • v.24 no.6
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    • pp.1064-1071
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    • 2019
  • Multiview stereo matching algorithm is used to reconstruct 3D shape from a set of 2D images. Conventional multiview stereo algorithms have been implemented on high-performance hardware due to the heavy complexity that contains a large number of calculations in each step. However, as the performance of mobile graphics processors has recently increased rapidly, complex computer vision algorithms can now be implemented on mobile devices like a smartphone and an embedded board. In this paper we parallelize an multiview stereo algorithm using OpenCL on mobile GPU and provide various optimization techniques on the embedded hardware with limited resource.

Design of a Small Loop Microstrip Antenna to load Capacitors (용량을 장하한 미소 루프 마이크로스트립 안테나 설계)

  • Park Seong-Il;Ko Young-Hyuk
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.637-640
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    • 2006
  • In this paper, a microstrip antenna with a small loop consisting of the left and right parallel plate to load capacitor is proposed. It is obtained the improved small size than the antenna of the transformed Uh and the antenna of the left and right parallel plate to load capacitor on QMSA. Equivalent circuit of transmission line model is designed to find more accurate resonant frequency. Also, the designed and fabricated antenna can receive both vertically and horizontally polarized waves to operating frequency of 1.5GHz. Therefore proposed antenna is available as a small antenna for wireless communication and will be quite useful for indoor communication

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