• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• Journal of Power Electronics
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• 제11권4호
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• pp.533-541
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• 2011

The redundant operation of a parallel AC to DC converter via a serial communication bus is presented. The proposed system consists of three isolated CUK power factor correction modules. The controller for each converter is a dsPIC30F6010 microcontroller while a RS485 communication bus and the clock signal are used for synchronizing the data communication. The control strategy of the redundant operation relies on the communication of information among each of the modules, which communicate via a RS485 serial bus. This information is received from the communication checks of the converter module connected to the system to share the load current. Performance evaluations were conducted through experimentation on a three-module parallel-connected prototype, with a 578W load and a -48V dc output voltage. The proposed system has achieved the following: the current sharing is quite good, both the transient response and the steady state. The converter modules can perform the current sharing immediately, when a fault is found in another converter module. In addition, the transient response occurs in the system, and the output voltages are at their minimum overshoot and undershoot. Finally, the proposed system has a relatively simple implementation for the redundant operation.

• International Journal of Contents
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• 제9권1호
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Journal of Communications and Networks
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• 제16권4호
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• pp.436-446
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• 2014

The high intensity of research and modeling in fields of mathematics, physics, biology and chemistry requires new computing resources. For the big computational complexity of such tasks computing time is large and costly. The most efficient way to increase efficiency is to adopt parallel principles. Purpose of this paper is to present the issue of parallel computing with emphasis on the analysis of parallel systems, the impact of communication delays on their efficiency and on overall execution time. Paper focuses is on finite algorithms for solving systems of linear equations, namely the matrix manipulation (Gauss elimination method, GEM). Algorithms are designed for architectures with shared memory (open multiprocessing, openMP), distributed-memory (message passing interface, MPI) and for their combination (MPI + openMP). The properties of the algorithms were analytically determined and they were experimentally verified. The conclusions are drawn for theory and practice.

• 한국인터넷방송통신학회논문지
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• 제9권1호
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• pp.39-45
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• 2009

본 논문에서는 최근 무선 통신 시스템에서 빠른 데이터전송 방식으로서 사용되고 있는 OFDM 통신방식의 저소비전력화 방안을 제안한다. 일반적으로 OFDM에서 주요 신호처리 방식은 디지털을 이용한 프리에 변환이다. 이런 디지털 프리에 변환은 많은 소비전력이 필요하며 이것은 무선통신 시스템에 있어서 커다란 제약이 되고 있다. 전류모드를 이용한 아날로그 프리에 변환(FFT) LSI는 이러한 소비전력의 문제를 해결할 수 있는 주요 대안으로 떠오르고 있다. 그러나 이러한 신호처리 방식을 사용하기 위해서는 전류모드를 이용한 직병렬/병직렬 변환기(Serial-to-Parallel/Parallel-to-Serial Converter)가 필수적으로 필요하다. 본 논문에서는 전류모드로 구성한 아날로그 프리에 변환(FFT) LSI를 이용해 수신단의 저소비전력을 실현하기 위해 필수적인 새로운 전류모드 직병렬/병직렬 변환기를 제시하였으며 설계된 칩의 측정결과가 시뮬레이션 결과와 일치하는 것을 확인하였다. 제안된 전류모드 직병렬/병직렬 변환기의 개발로 저소비전력에 큰 장점을 지니고 있는 아날로그 FFT LSI의 활용이 가능해졌으며 송수신단 시스템에서 큰 소비전력의 감소효과를 가져올 것으로 기대된다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2011년도 춘계학술발표대회
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• pp.156-157
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• 2011

In this work, we study the checkpoint/restart problem for message-passing parallel applications running on cloud computing environment. This is a new direction which arises from the trend of enabling the applications to run on the cloud computing environment. The main objective is to propose an efficient checkpoint algorithm for message-passing parallel applications considering communications with external systems. We further implement the novel algorithm by modifying gSOAP and OpenMPI (the open source libraries) which support service calls and checkpoint message-passing parallel programs, especially. The simulation showed that additional costs to the executing and checkpointing application of the algorithm are negligible. Ultimately, the algorithm supports efficiently the checkpoint/restart service for message-passing parallel applications, that send requests to external services.

• Journal of Electrical Engineering and Technology
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• 제3권3호
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• pp.408-421
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• 2008

In this paper, the parallel operation for a FC generation system is introduced and designed in order to increase the capacity for the distributed generation of a proton exchange membrane fuel cell (PEMFC) system. The equipment is the type that is used by parallel operated PEMFC generation systems which have two PEMFC systems, two dc/dc boost converters with shared dc link, and a grid-connected dc/ac inverter for embedded generation. The system requirement for the purpose of parallel operated generation using PEMFC system is also described. Aspects related to the mechanical (MBOP) and electrical (EBOP) component, size, and system complexity of the distributed generation system, it is explained in order to design an optimal distributed generation system using PEMFC. The optimal controller design for the parallel operation of the converter is suggested and informative simulations and experimental results are provided.

• Journal of Information Processing Systems
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• 제7권2호
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• pp.271-286
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• 2011

In this paper, we propose efficient algorithms for parallel prefix computation and sorting on a recursive dual-net. The recursive dual-net $RDN^k$(B) for k > 0 has $(2n_o)^{2K}/2$ nodes and $d_0$ + k links per node, where $n_0$ and $d_0$ are the number of nod es and the node-degree of the base-network B, respectively. Assume that each node holds one data item, the communication and computation time complexities of the algorithm for parallel prefix computation on $RDN^k$(B), k > 0, are $2^{k+1}-2+2^kT_{comm}(0)$ and $2^{k+1}-2+2^kT_{comp}(0)$, respectively, where $T_{comm}(0)$ and $T_{comp}(0)$ are the communication and computation time complexities of the algorithm for parallel prefix computation on the base-network B, respectively. The algorithm for parallel sorting on $RDN^k$(B) is restricted on B = $Q_m$ where $Q_m$ is an m-cube. Assume that each node holds a single data item, the sorting algorithm runs in $O((m2^k)^2)$ computation steps and $O((km2^k)^2)$ communication steps, respectively.

• 한국정보과학회논문지:시스템및이론
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• 제29권12호
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• pp.655-664
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• 2002

데이타 병렬 모델은 대규모 병렬성을 용이하게 얻을 수 있는 장점이 있지만, 데이타 분산으로 인한 통신 지연시간은 상당한 부담이 된다. 본 논문에서는 데이타 병렬 프로그램에 내재되어 있는 태스크 병렬성을 추출하여 이러한 통신 지연시간을 감추는데 이용할 수 있음을 보인다. 기존의 태스크 병렬성 추출은 데이타 병렬성을 고려하지 않았지만, 여기서는 데이타 병렬성을 그대로 유지하면서 태스크 병렬성을 활용하는 방법에 대해 설명한다. 데이타 병렬 루프를 포함할 수 있는 다수의 태스크 스레드들로 구성된 다중스레드 프로그램을 표현하기 위해 본 논문에서는 PCFG(Parallel Control Flow Graph)라는 표현 형태를 제안한다. PCFG는 단일 스레드인 원시 데이타 병렬 프로그램으로부터 HDG(Hierarchical Dependence Graph)를 통해 생성될 수 있으며, 또한 PCFG로부터 다중스레드 코드를 쉽게 생성할 수 있다.

• 센서학회지
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• 제24권3호
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.