• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.8
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• pp.1770-1785
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• 2013

In this paper, a multi-hop transmission protocol based on parallel communication of secondary users (SUs) is proposed. The primary multi-hop network coexists with a set of SUs by cooperative spectrum sharing. The main optimization target of our protocol is the overall performance of the secondary system with the guarantee of the primary outage performance. The energy consumption of the primary system is reduced by the cooperation of SUs. The aim of the primary source is to communicate with the primary destination via a number of primary relays. SUs may serve as extra decode-and-forward relays for the primary network. When an SU acts as a relay for a primary user (PU), some other SUs that satisfy the condition for parallel communication are selected to simultaneously access the primary spectrum for secondary transmissions. For the proposed protocol, two opportunistic routing strategies are proposed, and a search algorithm to select the SUs for parallel communication is described. The throughput of the SUs and the PU is illustrated. Numerical results demonstrate that the average throughput of the SUs is greatly improved, and the end-to-end throughput of the PU is slightly increased in the proposed protocol when there are more than seven SUs.

• The Transactions of the Korea Information Processing Society
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• v.4 no.10
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• pp.2544-2552
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• 1997

This paper presents three multiprocess models for parallel protocol implementation, that is, (1)channel communication model, (2)fork-join model, and (3)event polling model. For the specification of parallelism for each model, a parallel programming language, Par. C System, is used. to measure the performance of multiprocess models, we implemented the Internet Protocol Suite(IPS) Internet Protocol (IP) for each model by writing the parallel language on the Transputer. After decomposing the IP functions into two parts, that is, the sending side and the receiving side, the parallelism in both sides is exploited in the form of Multiple Instruction Single Data (MISD). Three models are evaluated and compared on the basis of various run-time overheads, such as an event sending via channels in the parallel channel communication model, process creating in the fork-join model and context switching in the event polling model, at the sending side and the receiving side. The event polling model has lower processing delays as about 77% and 9% in comparison with the channel communication model and the fork-join model at the sending side, respectively. At the receiving side, the fork-join model has lower processing delays as about 55% and 107% in comparison with the channel communication model and the event polling model, respectively.

• Journal of information and communication convergence engineering
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• v.17 no.4
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• pp.267-273
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• 2019

South Korea has allowed parallel importation since 1995. Parallel importation causes competition among importers in the logistics process allowing, consumers to purchase foreign brand products at low prices. Most parallel importers base product pricing on subjective judgements. Fashion products in particular, have different sales rates depending on trends and seasons, so sales performance varies greatly depending on selling price timing and policy. The merchandiser (MD) set the price on parallel importation products by aggregating information on imported products and pricing goods. However, this customized process is very time consuming for the MD. This is because the logistics process of parallel importation's customs clearance procedures and repair works is complicated and takes a significant amount of time. In this paper, we propose an improved parallel importation logistics process based on big data, which automatically sets the price of parallel importation products.

• Journal of KIISE:Databases
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• v.29 no.1
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• pp.58-71
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• 2002

Generally, multi-dimensional data such as image and spatial data require large amount of storage space. There is a limit to store and manage those large amount of data in single workstation. If we manage the data on parallel computing environment which is being actively researched these days, we can get highly improved performance. In this paper, we propose a parallel high-dimensional index structure that exploits the parallelism of the parallel computing environment. The proposed index structure is nP(processor)-n$\times$mD(disk) architecture which is the hybrid type of nP-nD and lP-nD. Its node structure increases fan-out and reduces the height of a index tree. Also, A range search algorithm that maximizes I/O parallelism is devised, and it is applied to K-nearest neighbor queries. Through various experiments, it is shown that the proposed method outperforms other parallel index structures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.48-55
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• 2009

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.

• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.485-490
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• 2017

In this paper, we propose a technique for high speed removal of sea-fog using a graphic processor. This technique uses a host processor(CPU) and several graphics processors(GPU) capable of parallel processing to remove sea-fog from the input image. In the process of removing sea-fog, the dark channel extraction, the maximum brightness channel extraction, and the calculation of the transmission are performed by the host processor, and the process of refining the transmission by applying the bidirectional filter is performed in parallel through the graphic processor. To verify the proposed parallel processing method, three NVIDIA GTX 1070 GPUs were used to construct the verification environment. As a result, it takes about 140ms when implemented with one graphics processor, and 26ms when implemented using OpenMP and multiple GPGPUs. The proposed a parallel processing algorithm based on the graphics processor unit can be used for safe navigation, port control and monitoring system.

• Journal of the Korea Society for Simulation
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• v.7 no.1
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• pp.69-83
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• 1998

In this paper, we present the results of simulation by running parallel VHDL simulation on typical MPP(Massively Parallel Processor) systems such as IBM SP2 and SGI Origin 2000. Parallel simulation uses the synchronous protocol and parallel program is implemented using MPI(Message Passing Interface) based on message passing model, so that it can urn on any parallel programming environment which supports MPI, a standard communication library. And then GVT(Global Virtual Time) computation for parallel simulation is based on the global broadcasting with MPI＿Bcast(), which is a standard function in MPI and piggybacking. Our benchmark exhibits that as size of VHDL grows, the parallel simulation has a better performance compared with the sequential simulation. In addition, we also show the results of comparison between IBM SP2 and SGI Origin 2000 by applying the same application to those indirectly.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• ETRI Journal
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• v.46 no.2
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• pp.194-204
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• 2024

A new method is proposed to generate a 32-tupling frequency millimeter wave (MMW) with eight Mach-Zehnder modulators (MZMs) connected in parallel. Theoretical analyses and simulation experiments are conducted. The optical sideband suppression ratio (OSSR) of the obtained ±16th order optical sidebands are 61.54 dB and 61.42 dB, and the radio frequency spurious suppression ratios (RFSSRs) of the generated 32-tupling frequency MMW are 55.52 dB and 55.27 dB based on the theoretical analysis and simulation experiments, respectively; these outcomes verified the feasibility of the new method. The main parameters used to affect the stability of the generated signal are the modulation index and extinction ratio of MZM. Their effects on the OSSR and RFSSR of the generated signals are investigated when they deviate from their designed values. Compared with the other proposed methods for the generation of 32-tupling frequency MMW by MZM, our method has the best spectral purity and stability, and it is expected to have important MMW over fiber applications.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.3
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• pp.209-216
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• 2011

Recently the design of SoCs(System-on-Chips) in which TCM is embedded for high speed operation increases rapidly. In this paper, a parallel test structure for eDRAM-based TCM embedded in SoCs is proposed. In the presented technique, the MUT (Memory Under Test) is changed to parallel structure and it increases testability of MUT with boundary scan chains. The eDRAM is designed in structure for parallel test so that it can be tested for each modules. Dynamic test can be performed based on input-output data. The proposed techniques are verified their performance by circuits simulation.