• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1219-1224
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• 1999

This paper derived Montgomery's parallel algorithms for modular multiplication based on Walter's and Iwamura's method, and compared data dependence graph of each parallel algorithm. Comparing the result, Walter's parallel algorithm has small computational index in data dependence graph, so it is selected and used to computed spatial and temporal pipelining diagrams with each projection direction for designing expansible bit-level systolic array. We also evaluated internal operation of proposed expansible systolic array C++ language.

• ETRI Journal
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• v.26 no.5
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• pp.413-422
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• 2004

This paper investigates the impacts of array weight errors (AWE) in an antenna array (AA) on a parallel interference cancellation (PIC) receiver in uplink synchronous and asynchronous direct sequence code division multiple access (DS-CDMA) systems. The performance degradation due to an AWE, which is approximated by a Gaussian distributed random variable, is estimated as a function of the variance of the AWE. Theoretical analysis, confirmed by simulation, demonstrates the tradeoffs encountered between system parameters such as the number of antennas and the variance of the AWE in terms of the achievable average bit error rate and the user capacity. Numerical results show that the performance of the PIC with the AA in the DS-CDMA uplink is sensitive to the AWE. However, either a larger number of antennas or uplink synchronous transmissions have the potential of reducing the overall sensitivity, and thus improving its performance.

• Progress in Superconductivity and Cryogenics
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• v.10 no.1
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• pp.32-36
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• 2008

An HTS conductor with parallel HTS tapes is essential for a large power HTS device to flow a large current. One of the most important factor for this conductor is a current distribution. Non-uniform current distribution in parallel tapes makes the critical current of the conductor low and the AC losses high. In this paper we proposed a non-contact method which measured each current in parallel tapes by using an array of Hall sensors. A matrix can be derived from this array for calibration. The current distributions of 4 and 6 parallel tapes were measured.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12B
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• pp.1724-1732
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• 2001

In this paper, a technique for increasing the bandwidth of microstrip array antennas using the parallel coupled lines on a single layer is presented. Four types of wideband microstrip array antenna are designed and the characteristics of each type are analyzed. In addition, an iterative method using a distributed network is proposed to design the parallel coupled lines as a wideband impedance matching network. Measurements show that the proposed antennas provide wider bandwidths ∼1.7 times those of conventional microstirp array antennas, while the sizes of proposed antennal are the same as that of a conventional array. And low cross-polarization level can be obtained through symmetrical locations of the parallel coupled lines section

• International Journal of Contents
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• v.9 no.1
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• Journal of the Korean Solar Energy Society
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• v.29 no.2
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• pp.8-13
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• 2009

In this paper, two configurations of PV array are analyzed and tested under shading condition, where two configurations are series-parallel and total-crass-tied configuration. Each photovoltaic module is emulated by two 5 inch po1y-crystalline cells in series and an array is constructed by connecting 24 of the modules to compare a generated maximum power of the two configurations. Pspice and Sun simulator. PASAN IIIb, are used for simulation and experiment to test the array under various partial shading conditions. Test results show the total-cross-tied configuration generates 7.63% higher maximum power than the series-parallel configuration, and it is well matched to the analysis and simulations of the two configurations.

• Journal of Power Electronics
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• v.11 no.6
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• pp.870-879
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• 2011

Regulated peak power tracking (RPPT) systems such as the series structure and the series-parallel structures are commonly used in satellite space power systems. However, these structures process the solar array power or the battery power to the load through two cascaded regulators during one orbit cycle, which reduces the energy transfer efficiency. Also the battery charging time is increased due to placement of converter between the battery and the solar array. In this paper a parallel structure has been proposed which can improve the energy transfer efficiency and the battery charging time for satellite space power RPPT systems. An analogue controller is used to control all of the required functions, such as load voltage regulation and solar array stabilization with maximum power point tracking (MPPT). In order to compare the system efficiency and the battery charging efficiency of the proposed structure with those of a series (conventional) structure and a simplified series-parallel structure, simulations are performed and the results are analyzed using a loss analysis model. The proposed structure charges the battery more quickly when compared to the other two structures. Also the efficiency of the proposed structure has been improved under different modes of solar array operation when compared with the other two structures. To verify the system, experiments are carried out under different modes of solar array operation, including PPT charge, battery discharge, and eclipse and trickle charge.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.98-107
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• 1996

In this paper, we propose a scheme that maps the time-delay neural network (TDNN) into the neurocomputer called EMIND-II which has the wavefront toroidal mesh-array structure. This neurocomputer is scalable, consists of many timeshared virtual neurons, is equipped with programmable on-chip learning, and is versatile for building many types of neural networks. Also we define the programming model of this array and derive the parallel algorithms about TDNN for the proposed neurocomputer EMIND-II. In addition, the computational complexities for the parallel and serial algorithms are compared. Finally, we introduce an application of this neurocomputer to word recognition.

• Broadcasting and Media Magazine
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• v.6 no.2
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• pp.84-101
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• 2001

In this paper, we present a primitive system design of a super multi-view(SMV) 3-D display system based on a focused light array(FLA) concept using reflective vibrating scanner array(ViSA). The parallel beam scanning using a vibrating scanner array is performed by moving left and right an array of curvature-compensated mirrors or diamond-ruled reflective grating attached to a vibrating membrane. The parallel laser beam scanner array can replace the polygon mirror scanner which has been used in the SMV 3-D display system based on the focused light array(FLA) concept proposed by Kajiki at TAO(Telecommunications) Advancement Organization). The proposed system has great advantages in the sense that it requires neither huge imaging optics nor mechanical scanning pals. Some mathematical analyses and fundamental limitations of the proposed system are presented. The proposed vibrating scanner array, after some modifications and refinements, may replace polygon mirror-based scanners in the near future.