• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.6
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• pp.955-961
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• 2017

In this paper, we propose a parallel approximate string matching algorithm with k-mismatches for multiple fixed-length patterns (PMASM) in DNA sequences. PMASM is developed from parallel single pattern approximate string matching algorithms to effectively calculate the Hamming distances for multiple patterns with a fixed-length. In the preprocessing phase of PMASM, all target patterns are binary encoded and stored into a look-up memory. With each input character from the input string, the Hamming distances between a substring and all patterns can be updated at the same time based on the binary encoding information in the look-up memory. Moreover, PMASM adopts graphics processing units (GPUs) to process the data computations in parallel. This paper presents three kinds of PMASM implementation methods in GPUs: thread PMASM, block-thread PMASM, and shared-mem PMASM methods. The shared-mem PMASM method gives an example to effectively make use of the GPU parallel capacity. Moreover, it also exploits special features of the CUDA (Compute Unified Device Architecture) memory structure to optimize the performance. In the experiments with DNA sequences, the proposed PMASM on GPU is 385, 77, and 64 times faster than the traditional naive algorithm, the shift-add algorithm and the single thread PMASM implementation on CPU. With the same NVIDIA GPU model, the performance of the proposed approach is enhanced up to 44% and 21%, compared with the naive, and the shift-add algorithms.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.27-36
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• 1999

This paper proposes algorithms that design the highly parallel multiple-valued logic circuit of DTG(Directed Tree Graph) to be represented by tree structure relationship between input and output of nodes. The conventional Nakajima's algorithms have some problems so that this paper introduce the concept of mathematical analysis based on tree structure to design optimized locally computable circuit. Using the proposed circuit design algorithms in this paper it is possible to design circuit in that DTG have any node number - not to design by Nakajima's algorithms. Also, making a comparison between the circuit design using Nakajim's algorithms and this paper's, we testify that proposed algorithms in this paper optimizes circuit design all case of DTG. Some examples are shown to demonstrate the usefulness of the circuit design algorithm.

• Journal of the Korean Operations Research and Management Science Society
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• v.39 no.4
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• pp.19-31
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• 2014

We study parallel processing techniques for the R programming language of high performance computing technology. In this study, we used massively parallel computing system which has 25,408 cpu cores. We conducted a performance evaluation of a distributed memory system using MPI and of a the shared memory system using OpenMP. Our findings are summarized as follows. First, For some particular algorithms, parallel processing is about 150 times faster than serial processing in R. Second, the distributed memory system gets faster as the number of nodes increases while shared memory system is limited in the improvement of performance, due to the limit of the number of cpus in a single system.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.05a
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• pp.235-240
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• 2007

A large power fuel cell generation system needs a parallel operation of de-de boost converter. Therefore, this paper proposed parallel operation algorithms of de-de boost converters for the large scale fuel cell generation system of 250[kW] and the operating principle along with the control method in detail. This paper uses a maximum current sharing method as a parallel operation method and also the phase shift full bridge de-de converter as a de-de boost converter. Simulation and experimental results on two prototype converter modules of 500W show that the parallel operation method can be applied to the 250[kW] power converter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.5
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• pp.163-169
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• 2006

In order to use parallel computers in specific applications, algorithms need to be developed and mapped onto parallel computer architectures. Main memory access for shared memory system or global communication in message passing system deteriorate the computation speed. In this paper, it is found that the m-step generalization of the block Lanczos method enhances parallel properties by forming in simultaneous search direction vector blocks. QR factorization, which lowers the speed on parallel computers, is not necessary in the m-step block Lanczos method. The m-step method has the minimized synchronization points, which resulted in the minimized global communications and main memory access compared to the standard methods.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2001.04a
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• pp.61-68
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• 2001

A parallel nonlinear analysis program of prestressed concrete frame is migrated on a PC cluster system and a massively parallel processing system, CRAY T3E system, using MPI. The PC cluster system is configured with Pentium Ⅲ class PCs and fast ethernet. The CRAY T3E system is composed of a set of nodes each containing one Processing Element (PE), a memory subsystem and its distributed memory interconnect network. Parallel computing algorithms are implemented on element-wise processing parts including the calculation of stiffness matrix, element stresses and determination of material states, check of material failure and calculation of unbalanced loads. Parallel performance of the migrated program is evaluated through typical numerical examples.

• Journal of the Korea Safety Management & Science
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• v.13 no.3
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• pp.107-114
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• 2011

Traveling salesman problem is to minimize the total cost for a traveling salesman who wants to make a tour given finite number of cities along with the cost of travel between each pair them, visiting each cities exactly once before returning home. Traveling salesman problem is known to be NP-hard, and it needs a lot of computing time to get the optimal solution, so that heuristics are more frequently developed than optimal algorithms. This study suggests a hybrid parallel genetic algorithm(HPGA) for traveling salesman problem The suggested algorithm combines parallel genetic algorithm, nearest neighbor search, and 2-opt. The suggested algorithm has been tested on 7 problems in TSPLIB and compared the results of existing methods(heuristics, meta-heuristics, hybrid, and parallel). Experimental results shows that HPGA could obtain good solution in total travel distance minimization.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.4
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• pp.341-349
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• 2004

A parallel operation of Uninterruptible Power Supply(UPS) systems is used to increase power capacity of the system or to secure higher reliability at critical loads. In the conventional parallel operation, the load-sharing control to maintain the current balance is the most important, since the load-sharing is very sensitive to discord between components of each module, amplitude/phase difference, line impedance, output LC filter, and so on. To solve these problems various control algorithms are researching. However, these methods cannot apply to the different ratings of UPS. In the case, master and slave control algorithm for parallel operation is adequate. However, if the UPS ratings are different, the value of passive filters L, C is different, and it affects the sharing of current. This paper presents general problems of conventional parallel operation systems, and control strategy for parallel operation with different ratings. The validity of the proposed control strategy is investigated through simulation and experiment in the parallel operation system with two 3-phase UPS systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.442-449
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• 2005

In this paper, we introduce three kinds of simplified high-speed decoding algorithms for turbo product decoder. First, A parallel decoder structure, the row and column decoders operate in parallel, is proposed. Second, HAD(Hard Decision Aided) algorithm is used for early-stopping algorithm. Lastly, P-Parallel TPC decoder is a parallel decoding scheme, processing P rows and P columns in parallel instead of decoding one by one as that in the original scheme.