• Earthquakes and Structures
• /
• 제7권6호
• /
• pp.1001-1024
• /
• 2014

The size of spread footings was found to be unnecessarily large from some actual engineering practices constructed in Taiwan, due to the strict design provisions related to footing uplift. According to the earlier design code in Taiwan, the footing uplift involving separation of footing from subsoil was permitted to be only up to one-half of the foundation base area, as the applied moment reaches the value of plastic moment capacity of the column. The reason for this provision was that rocking of spread footings was not a favorable mechanism. However, recent research has indicated that rocking itself may not be detrimental to seismic performance and, in fact, may act as a form of seismic isolation mechanism. In order to clarify the effects of the relative strength between column and foundation on the rocking behavior of a column, six circular reinforced concrete (RC) columns were designed and constructed and a series of rocking experiments were performed. During the tests, columns rested on a rubber pad to allow rocking to take place. Experimental variables included the dimensions of the footings, the strength and ductility capacity of the columns and the intensity of the applied earthquake. Experimental data for the six circular RC columns subjected to quasi-static and pseudo-dynamic loading are presented. Results of each cyclic loading test are compared against the benchmark test with fixed-base conditions. By comparing the experimental responses of the specimens with different design details, a key parameter of rocking behavior related to footing size and column strength is identified. For a properly designed column with the parameter higher than 1, the beneficial effects of rocking in reducing ductility and the strength demand of columns is verified.

• Transactions on Electrical and Electronic Materials
• /
• 제12권3호
• /
• pp.115-118
• /
• 2011

Process characterization of the chemical mechanical polishing (CMP) process for undensified phosphosilicate glass (PSG) film is reported using design of experiments (DOE). DOE has been addressed to experimenters to understand the relationship between input variables and responses of interest in a simple and efficient way. It is typically beneficial for determining the adequate size of experiments with multiple process variables and making statistical inferences for the responses of interests. Equipment controllable parameters to operate the machine include the down force (DF) of the wafer carrier, pressure on the backside of the wafer, table and spindle speed (SS), slurry flow rate, and pad condition. None of them is independent; thus, the interaction between parameters also needs to be indicated to improve process characterization in CMP. In this paper, we have selected the five controllable equipment parameters, such as DF, back pressure (BP), table speed (TS), SS, and slurry flow (SF), most process engineers recommend to characterize the CMP process with respect to material removal rate (RR) and film uniformity as a percentage. The polished material is undensified PSG. PSG is widely used for the plananization in multi-layered metal interconnects. We identify the main effect of DF, BP, and TS on both RR and film uniformity, as expected, by the statistical modeling and analysis on the metrology data acquired from a series of $2^{5-1}$ fractional factorial design with two center points. This revealed the film uniformity of the polished PSG film contains two and three-way interactions. Therefore, one can easily infer that the process control based on better understanding of the process is the key to success in semiconductor manufacturing, typically when the wafer size reaches 300 mm and is continuously scheduled to expand up to 450 mm in or little after 2012.

• Tribology and Lubricants
• /
• 제31권4호
• /
• pp.141-147
• /
• 2015

Gas foil thrust bearings (GFTBs) have attractive advantages over rolling element bearings and oil film thrust bearings, such as oil-free operation, high speed stability, and high-temperature operation. However, GFTBs have lower load carrying capacity than the other two types of bearings owing to the inherent low gas viscosity. The load carrying capacity of GFTBs depends mainly on the compliance of the foil structure and the formed hydrodynamic wedge, where the gas pressure field is generated between the top foil and the thrust runner. The load carrying capacity of the GFTBs is very important for the suitable design of oil-free turbomachinery with high performance. The aim of the present study is to identify the characteristics of the load carrying performance of GFTBs. A new test rig for the experimental measurements is designed to provide static loads up to 800 N using a pneumatic cylinder. The maximum operating speed of the driving motor is 30,000 rpm. A series of experimental tests—lift-off test, static load performance test, and maximum load capacity test—estimate the performance of a six-pad GFTB, in terms of the static load, driving torque, and temperature. The maximum load capacity is determined by increasing the static load until the driving torque rises suddenly with a sharp peak. The test results show that the torque and temperature increase linearly with the static load. The estimated maximum load capacity per unit area is approximately 80.5 kPa at a rotor speed of 25,000 rpm. The test results can be used as a design guideline for GFTBs for realizing oil-free turbomachinery.

• 마이크로전자및패키징학회지
• /
• 제17권1호
• /
• pp.47-53
• /
• 2010

본 연구에서는 솔더 페이스트를 이용한 프린팅 공정의 해석에 대해 연구를 수행하였다. 스텐실 프린팅 공정의 설계에서 중요한 인자는 프린팅 조건, 스텐실 설계, 그리고 솔더 페이스트의 물성 등이다. 본 연구에서는 이 인자들 중에서, 솔더 페이스트의 점도와 표면장력, 그리고 솔더 페이스트와 스텐실 사이의 접촉각이 프린팅 공정의 성능에 미치는 영향을 해석을 통해 파악하였다. 실제 해석에 앞서 압력에 의해서 솔더 페이스트가 스텐실에 채워지는 단순화된 형상과 조건으로 해석을 수행하였다. 해석은 마이크로 유동의 해석에 많이 이용이 되고 있는 상용 소프트웨어인 콤솔(COMSOL)을 이용하였고 축대칭으로 해석하였다. 해석 결과, 솔더 페이스트의 점도는 충진률에 큰 영향을 줌을 알 수 있었고 표면장력과 접촉각은 충진되는 형상에 영향을 줌을 알 수 있었다.

• 한국항행학회논문지
• /
• 제25권1호
• /
• pp.40-51
• /
• 2021

본 논문에서는 도심항공 모빌리티(UAM) 시스템을 국내에서 운용하기 위해 필요한 국내외 규정을 분석하여 수직이착륙장의 설계 요구 조건을 도출하고 이착륙 패드의 크기를 규정하였으며, 이를 바탕으로 수직이착륙장 형상을 제안하였다. 먼저, 인구 밀집도가 높은 수도권에 대해 국토교통부에서 제시한 실증노선을 기준으로 수직이착륙장의 시범 위치를 선정하고 각 위치의 특징을 분석하였으며 크기를 측정하여 수직이착륙장의 설치 가능 수를 파악하였다. 이후 수직이착륙장 운영에 필요한 변수들을 설정하여 동시운용과 주기장 수에 따른 시간당, 하루, 한 달 동안의 항공기 운용 가능 대수, 수용 가능 인원, 효율성 등을 계산하였다. 마지막으로, CATIA를 사용하여 가상의 수직이착륙장 형상을 설계요구조건을 적용하여 구현하였다.

• 한국의류학회지
• /
• 제46권4호
• /
• pp.657-671
• /
• 2022

This study aims to develop three dimensional (3D) yoga knee protectors that provide excellent wearing comfort. Three types of pads were modeled using 3D human data: two types of 3.0-cm-wide pads separated into top and bottom with thicknesses of 0.1 cm (TPU-1: A) and 0.2 cm (TPU-2: B); and one type with three 0.2-cm-thick separated panels (TPU-S: C). Based on these models, five knee protectors were developed using 3D patterning and 3D printing. Types A, B, and C were integrated with 0.6-cm neoprene pads. Type D was fabricated with a donut-shaped 0.6-cm neoprene pad inserted, while Type E consisted of two discrete 0.6-cm neoprene pads embedded in the protector's upper and lower sides. Wearing comfort was evaluated in terms of fit, pressure, and cushioning while in a standing and kneeling position and while in motion. The findings suggest that the fabricated knee protectors were evaluated as comfortable to the individuals with knee pain, rather than those without knee pain. The individuals with knee pain preferred the soft pads made of neoprene positioned around the knee (NEO-S: E), while those without knee pain favored the cushioned pads with a pattern structure maintained by thin 3D-printed pads (TPU-1: A).

• 한국정보통신학회논문지
• /
• 제15권11호
• /
• pp.2457-2464
• /
• 2011

본 논문에서는 압전 소자를 이용한 진동에너지 하베스팅 회로를 설계하였다. 압전소자의 전력-전압 특성을 이용하여 최대 전력을 부하로 전달하기 위한 MPPT(Maximum Power Point Tracking) 제어 기능을 구현하였다. MPPT 제어 회로는 압전소자의 출력 단에 연결된 전파 정류회로의 개방회로 전압을 주기적으로 샘플링하여 최대 가용전력이 생성되는 지점을 추적하고 이를 부하로 전달하는 역할을 한다. 제안된 진동에너지 하베스팅 회로는 $0.18{\mu}m$ CMOS 공정으로 설계하였다. 모의실험 결과 설계된 회로의 최대 전력 효율은 91%이고, pad를 제외한 칩 면적은 $700{\mu}m{\times}730{\mu}m$이다.

• Tribology and Lubricants
• /
• 제12권4호
• /
• pp.18-27
• /
• 1996

An interlaboratory wear testing was performed in order to understand the friction behaviors and the wear mechanisms of the sintered composites. The specimens were the sintered bronze matrix composites having various contents of friction additives, friction control agents and reinforcements. The variation of the wear characteristics according to the constituents of the composites as well as the wear conditions was investigated by SEM, EPMA, OM, the hardness testing and the measurement of friction. The specimen having glass fiber as the matrix reinforcement showed a remarkable increase in wear resistance as increasing the content of glass fiber. Graphite particles in the composites exhibited the lubricating effect and also resulted in the lowering strength of the matrix. Addition of Mo powder to the composites led to the deterioration of wear properties at the room temperature, however, an enhanced wear properties were obtained in the containing Mo at an elevated temperature.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
• /
• pp.123-124
• /
• 2008

본 논문에서 설계한 온도센서는 $0.l8{\mu}m$ CMOS 공정으로 $-55^{\circ}C{\sim}125^{\circ}C$의 온도 범위에서 ${\pm}0.1^{\circ}C$의 정확도를 갖는다. 이 센서는 parasitic PNP 트랜지스터로 온도 변화에 따른 전압을 추출하고 시그마-델타 변조기를 이용하여 디지털 온도 값을 얻기 위한 비트스트림을 생성한다. 또한, 이상적이지 않은 요소로 인해 발생할 수 있는 에러를 $0.01^{\circ}C$ 레벨로 감소시키기 위해 DEM(Dynamic Element Matching)과 2차 시그마-델타 변조기를 이용하였고, Bandgap Reference 회로로 온도 변화에 상관없이 일정한 bias 전압을 생성한다. 설계된 온도센서의 면적은 PAD를 포함하여 $0.98mm{\times}0.92mm$이고, 1.8V 단일 전원에서 동작한다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
• /
• pp.509-510
• /
• 2008

본 논문은 $0.18{\mu}m$ CMOS 공정을 사용하여 2.5Gb/s CMOS CDR을 설계하였다. CML type의 논리게이트를 이용하여 보다 높은 주파수의 대역의 데이터를 복원하기 위한 위상비교기(PD)와 PD의 up과 down신호를 지연없이 루프필터(LF)에 공급하기 위한 전하점프(CP) 그리고 외부 스위치를 통해 VCO이득을 조절할 수 있는 링 타입의 VCO로 구성되었다. 또한 VCO의 부담을 줄이기 위하여 half-rate 클럭 테크닉을 사용하였다. Cadence tool을 사용하여 모의실험 및 layout을 하였다. VCO이득은 100MHz/V이고, 클릭 jitter는 rising일 때 27ps, falling일 때 32ps로 우수한 결과를 얻을 수 있었다. 테스트칩 제작은 매그나침 $0.18{\um}$ CMOS 공정을 이용하였다. 칩 사이즈는 PAD를 포함하여 $850um{\times}750um$이다.