• Journal of the Korean Institute of Telematics and Electronics
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• v.5 no.3
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• pp.9-24
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• 1968

This report is concerned with the optimum design of hyper-aprupt p-n junctiea silion diode and fabriction of this diode usable for electrical tuning application. Impurity profile in the junction was assumed to clean exponential function. With this assunntion, an optimum criterion for designing standard AM radio tuning capacitor was derived. In the diffusion process, after aluminum and antimony as impurties were deposited in vacuum on a P-type silicon wafer, the diffusion was followed by loading the wafer into the high temperature furnace.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.332-340
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• 2023

Crystalline silicon solar cells have attracted great attention for their various advantages, such as the availability of raw materials, high-efficiency potential, and well-established processing sequence. Tunnel oxide passivated contact (TOPCon) solar cells are widely regarded as one of the most prospective candidates for the next generation of high-performance solar cells because an efficiency of 26% has been achieved in small-area solar cells. Compared to n-type TOPCon solar cells, the photo conversion efficiency (PCE) of p-type TOPCon is slightly higher. The highest PCEs of p-type TOPCon and n-type TOPCon solar cells are 26.0% and 25.8%, respectively. Despite the highest efficiency in small-area cells, limited progress has been achieved in p-type TOPCon solar cells for large are due to their lower carrier lifetime and inferior surface passivation with the boron-doped c-Si wafer. Nevertheless, it is of great importance to promoting the p-type TOPCon technology due to its lower price and well-established manufacturing procedures with slight modifications in the PERC solar cells production lines. The progress in different approaches to increase the efficiencies of p-type TOPCon solar cells has been reported in this review article and is expected to set valuable strategies to promote the passivation technology of p-type TOPCon, which could further increase the efficiency of TOPCon solar cells.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.662-666
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• 1989

Pure mono Silane(Purity: 99.99%) was used as a thin film source and [$SiH_4$ + $H_2$ (5%)] + [$PH_3$ + $H_2$(0.05%)] mixed dilute gas was used for p-n junction diode. The substrate was P-type silicon wafer (p=$3{\Omega}$ cm) with the direction (100). The crystalline qualities of deposited thin film were investigated by the X-ray diffraction, RHEED and TED patterns and the voltampere characteristics of p-n junction diode was identified by I-V curve.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.494-496
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• 1996

The purpose of this study is to investigate the effect of process conditions on pore distribution in porous silicon layer prepared by electrochemical reaction. Porous silicon layers formed on p-type silicon wafer show the network structure of fine porse whose diameters are less than 100${\AA}$. In n-type porous silicon, selective growth was found on the pore surface by wet etching process after PR patterning. And numerical method showed high current density on the pore tip. With this result we confirmed that pore formation has two steps. First step is the initial attack on the surface and second step is the directional growth on the pore tip.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.103.1-103.1
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• 2011

실리콘 이종접합 태양전지에서 계면 결함 밀도는 효율을 결정하는데 가장 중요한 요인으로 작용한다. 계면 결함은 캐리어의 재결합 위치로 작용하여, 계면 결함 밀도가 증가하면 재결합 속도가 증가하게 된다. 흡수층으로 사용되는 실리콘 웨이퍼 (결정질 실리콘)를 가능한 깨끗하게 세정함으로써, 또한 emitter로 쓰이는 비정질 실리콘을 낮은 데미지로 증착하여 계면 결함 밀도를 감소 시킬 수 있다. 이러한 계면 결함 밀도의 감소가 어떠한 변화로 인해 태양전지 특성에 영향을 주는지 시물레이션을 통해 알아보았다. n-type 웨이퍼에 p-type 비정질 실리콘을 emitter로 하여 TCO/p/i/n-type wafer/i/n/TCO/metal의 구조를 적용했고, wafer 전면과 i로 쓰인 무첨가된 비정질 실리콘 간의 계면 결함 밀도를 변수로 적용했다. 그 결과, 계면 결함 밀도가 감소함에 따라 재결합이 감소하여 태양전지 특성이 증가하는 측면도 있지만, 흡수층의 장벽 (barrier height)이 높아져 재결합을 더욱 감소시킴으로 인해 태양전지 특성이 증가함을 알 수 있었다.

• Advances in nano research
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• v.2 no.1
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• pp.1-14
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• 2014

Dislocations are basic crystal defects and represent one-dimensional native nanostructures embedded in a perfect crystalline matrix. Their structure is predefined by crystal symmetry. Two-dimensional, self-organized arrays of such nanostructures are realized reproducibly using specific preparation conditions (semiconductor wafer direct bonding). This technique allows separating dislocations up to a few hundred nanometers which enables electrical measurements of only a few, or, in the ideal case, of an individual dislocation. Electrical properties of dislocations in silicon were measured using MOSFETs as test structures. It is shown that an increase of the drain current results for nMOSFETs which is caused by a high concentration of electrons on dislocations in p-type material. The number of electrons on a dislocation is estimated from device simulations. This leads to the conclusion that metallic-like conduction exists along dislocations in this material caused by a one-dimensional carrier confinement. On the other hand, measurements of pMOSFETs prepared in n-type silicon proved the dominant transport of holes along dislocations. The experimentally measured increase of the drain current, however, is here not only caused by an higher hole concentration on these defects but also by an increasing hole mobility along dislocations. All the data proved for the first time the ambipolar behavior of dislocations in silicon. Dislocations in p-type Si form efficient one-dimensional channels for electrons, while dislocations in n-type material cause one-dimensional channels for holes.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.77-79
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• 2009

Amorphous/crystalline silicon heterojunction solar cells, TCO/a-Si:H (p)/c-Si(n)/a-Si:H(n)/Al, are investigated. The influence of various parameters for the front structures was studied. We used thin (10 nm) a-Si:H(p) layers of amorphous hydrogenated silicon are deposited on top of a thick ($500{\mu}m$) crystalline c-Si wafer. This work deals with the influence of the a-Si:H(p) doping concentration on the solar cell performance is studied.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.109-112
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• 2007

In this paper we describe a robust method of improving precision in monitoring high energy ion implantation processes. Ion implant energy accuracy was measured in the device manufacturing process using an unpatterned implanted layer on an intrinsic p-type silicon wafer. To increase Rs sensitivity to energy at the well implant process, a PN junction structure was formed by P-well and deep N-well implants into the p-type Si wafer. It was observed that the depletion layer formed by the PN junction was very sensitive to energy variation of the well implant. Conclusively, it can be recommended to monitor well implant processes using the Rs measurement method described herein, i.e., a PN junction diode structure since it shows excellent Rs sensitivity to variation caused by energy difference at the well implant step.

• Journal of Integrative Natural Science
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• v.8 no.1
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• pp.67-74
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• 2015

Sensing characteristics for porous smart particle based on DBR smart particles were reported. Optically encoded porous silicon smart particles were successfully fabricated from the free-standing porous silicon thin films using ultrasono-method. DBR PSi was prepared by an electrochemical etch of heavily doped $p^{++}$-type silicon wafer. DBR PSi was prepared by using a periodic pseudo-square wave current. The surface-modified DBR PSi was prepared by either thermal oxidation or thermal hydrosilylation. Free-standing DBR PSi films were generated by lift-off from the silicon wafer substrate using an electropolishing current. Free-standing DBR PSi films were ultrasonicated to create DBR-structured porous smart particles. Three different surface-modified DBR smart particles have been prepared and used for sensing volatile organic vapors. For different types of surface-modified DBR smart particles, the shift of reflectivity mainly depends on the vapor pressure of analyte even though the surfaces of DBR smart particles are different. However huge difference in the shift of reflectivity depending on the different types of surface-modified DBR smart particles was obtained when the vapor pressures are quite similar which demonstrate a possible sensing application to specify the volatile organic vapors.