• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.377-377
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• 2011

Organic solar cells (OSCs) with low cost have been studied to apply on flexible substrate by solution process in low temperature [1]. In previous researches, conventional organic solar cell was composed of metal oxide anode, buffer layer such as PEDOT:PSS, photoactive layer, and metal cathode with low work function. In this structure, indium tin oxide (ITO) and Al was generally used as metal oxide anode and metal cathode, respectively. However, they showed poor reliability, because PEDOT:PSS was sensitive to moisture and air, and the low work function metal cathode was easily oxidized to air, resulting in decreased efficiency in half per day [2]. Inverted organic solar cells (IOSCs) using high work function metal and buffer layer replacing the PEDOT:PSS have focused as a solution in conventional organic solar cell. On the contrary to conventional OSCs, ZnO and TiO2 are required to be used as a buffer layer, since the ITO in IOSC is used as cathode to collect electrons and block holes. The ZnO is expected to be excellent electron transport layer (ETL), because the ZnO has the advantages of high electron mobility, stability in air, easy fabrication at room temperature, and UV absorption. In this study, the IOSCs based on poly [N-900-hepta-decanyl-2,7-carbazole-alt-5,5-(40,70-di-2-thienyl-20,10,30-benzothiadiazole)] (PCDTBT) : [6,6]-phenyl C71 butyric acid methyl ester (PC70BM) were fabricated with the ZnO electron-transport layer and MoO3 hole-transport layer. Thickness of the ZnO for electron-transport layer was controlled by rotation speed in spin-coating. The PCDTBT and PC70BM were mixed with a ratio of 1:2 as an active layer. As a result, the highest efficiency of 2.53% was achieved.

• Journal of the Korean Vacuum Society
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• v.5 no.4
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• pp.327-332
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• 1996

In this study, the effects of $WSi_x$, thickness and fluorine concentration in tungsten polycide gate structure on gate oxide were investigated. As $WSi_x$, thickness increases, gate oxide thickness increases with fluorine incorporation in gate oxide, and time-to-breakdown($T_{BD,50%}$) of oxide decreases. The stress change with $WSi_x$ thickness was also examined. But it is understood that the dominant factor to degrade gate oxide properties is not the stress but the fluorine, incorporated during $WSi_x$ deposition, diffused into $WSiO_2$ after heat treatment. In order to understand the effect of fluorine diffusion into oxidem fluorine ion implanted gates were compared. The thickness variation and $T_{BD,50%}$ of gate oxide is saturated over 600 $\AA$ thickness of $WSi_x$. The TEM and SIMS studies show the microstructure less than 600 $\AA$ thickness is dense and flat in surface. However, over 600$\AA$, the microstructure of $WSi_x$ is divided into two parts: upper porous phase with rugged surface and lower dense phase with smmoth interface. And this upper phase is transformed into oxygen rich crystalline phase after annealing, and the fluorine is captured in this layer. Therefore, the fluorine diffusion into the gate oxide is saturated.

• Korean Journal of Materials Research
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• v.3 no.4
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• pp.352-360
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• 1993

A nitride layer was df'posited on the thermal oxide layer by LPCVD process. ONO(oxidenitricle oxide) capacitors with various thickness of component layer wore fabricated by wet reoxidation of the nitride with and without anrwalmg treatment and their properties were investigated. As a result of observation on the refrative index and etching behavior of the ONO fIlms, the nitride layer OF 40 A thick ness was not so dense that the bottom oxide during the reoxidation process and the capability of securing the capacitance decreased. The conduction current in the ONO multl-Iayer dielctric film was reduced as the bottom(or top) oxide layer became thicker. However, in the case of oxide with thickness more than 50A, it merely plays a factor of reduction in capacitance, and the effect of barrier for hole injection was not so much increased. Annealing of the nitride laypr bpfore reoxidation did not show a grpat effects on the refractive index and capacitance of the film, however, the annealing process increased the breakdown voltage by 2${\cdot}$V.

• Journal of Powder Materials
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• v.21 no.2
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• pp.114-118
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• 2014

In this study, an aluminum oxide layer for sealing treatment of nano-diamond powder was synthesized by anodizing under constant current. The produced pore size and oxide thickness were investigated using scanning electron microscopy. The pore size increased as the treatment time increased, current density increased, sulfuric acid concentration decreased, which is different from the results under constant voltage, due to a dissolution of the oxide layers. The oxide layer thickness by the anodizing increased as temperature, time, and current density increased. The results of this study can be applied to optimize the sealing treatment process of nano-diamond particles of 4-10 nm to enhance the resistances of corrosion and wear of the matrix.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.373-373
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• 2012

We fabricated conductive zinc oxide (ZnO) thin film at low temperature by UV-enhanced atomic layer deposition. The atomic layer deposition relies on alternate pulsing of the precursor gases onto the substrate surface and subsequent chemisorption of the precursors. In this experiment, diethylzinc (DEZ) and $H_2O$ were used as precursors with UV light. The UV light was very effective to improve the conductivity of the ZnO thin film. The thickness, transparency and resistivity were investigated by ellisometry, UV-visible spectroscopy and Four-point probe.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.539-542
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• 2001

In SiC semiconductor device processing, it needs high temperature anneal for activation of ion implanted dopants. The macrosteps, 7~8nm in height, are formed on the surface of SiC substrates during activation anneal. We have investigated the effect of thermally-grown SiO$_2$layer on the suppression of macrostep formation during high temperature anneal. The cap oxide layer was found to be efficient for suppression of macrostep formation even though the annealing temperature is as high as the melting point of SiO$_2$. The thin cap oxide layer (10nm) was evaporated during anneal then the macrosteps were formed on SiC substrate. On the other hand the thicker cap oxide layer (50nm) remains until the anneal process ends. In that case, the surface was smoother and the macrosteps were rarely formed. The thermally-grown oxide layer is found to be a good material for the suppression of macrostep formation because of its feasibility of growing and processing. Moreover, we can choose a proper oxide thickness considering the evaporate rate of SiO$_2$at the given temperature.

• Journal of the Korean Ceramic Society
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• v.37 no.3
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• pp.263-270
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• 2000

The Pt/copper oxide/n-Si electrodes were fabricated by depositing copper oxide thin film of 500${\AA}$ and very thin Pt layer on the n-type (100) Si substrate. hotoelectrochemical properties and stability profiles of the electrodes were investigated as a function of deposition time of Pt layer. As the deposition time of Pt layer increased up to 10 seconds, the photocurrent and quantum efficiency were increased and then decreased with further depositing time. The better cell stability was observed for the electrode with longer deposition time. The improvements in above photoelectrochemical properties indicate that Pt layer acts as a catalyst layer at electrode/electrolyte interface as well as a protective layer. The decreasing tendency of the photocurrent and efficiency for the electrode with Pt layer deposited above 20 seconds was explained as an increases in probbility of electron-hole pair recombination and also the absorbing photon loss at electrode surface due to the excessive thickness of Pt layer. The results were confirmed by impedance spectroscopy, mutiple cycle voltammograms and microstructural analyses.

• Journal of the Korean Society for Heat Treatment
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• v.7 no.3
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• pp.206-218
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• 1994

In 50%$NH_3+Air+N_2$ atmospheres, the effect of air additions on the growth characteristics of the compound layer during oxynitriding at $570^{\circ}C$ for 2hr in carbon and alloy steels has been investigated. The ammount of apparent residual ammonia during oxynitriding has shown to be increased with air additions(9~36 Vol. %) and X-ray diffraction analysis of case oxynitreded has shown that the compound layer consist of ${\varepsilon}-Fe_{2-3}$(N, C) phase and ${\gamma}^{\prime}-Fe_4$(N,C) phase. In the case of carbon steels, the thickness of oxide layer, compound layer and porous layer and the amount of ${\varepsilon}-Fe_{2-3}$(N,C) phase in the compound layer were increased with additions of air in 50%$NH_3+N_2$ atmospheres. At the same gas composition, the thickenss of oxide layer, compound layer and porous layer in alloy steels showed slightly thin layer thickness compared to those of carbon steels and the ${\gamma}^{\prime}-Fe_4$(N,C) phase in the compound layer of alloy steels was found barely. Therefore, the most obvious effect of air addition in the gas nitriding atmosphere has been found to in crease further kinetics of nitriding reaction.

• Transactions on Electrical and Electronic Materials
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• v.18 no.5
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• pp.250-252
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• 2017

High-performance full swing logic inverters were fabricated using amorphous 1 wt% Si doped indium-zinc-oxide (a-SIZO) thin films with different channel layer thicknesses. In the inverter configuration, the threshold voltage was adjusted by varying the thickness of the channel layer. The depletion mode (D-mode) device used a TFT with a channel layer thickness of 60 nm as it exhibited the most negative threshold voltage (-1.67 V). Inverters using enhancement mode (E-mode) devices were fabricated using TFTs with channel layer thicknesses of 20 or 40 nm with excellent subthreshold slope (S.S). Both the inverters exhibited high voltage gain values of 30.74 and 28.56, respectively at $V_{DD}=15V$. It was confirmed that the voltage gain can be improved by increasing the S.S value.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1621-1623
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• 1997

The breakdown voltage of SOI RESURF (REduce SURface Field) diode using a SIPOS (Semi Insulating POlycrystalline Silicon) layer is verified in terms of n-drift layer length and surface oxide thickness by device simulator MEDICI, and compared with conventional SOI RESURF diode. Increasing the n-drift layer length, the breakdown voltage of SOI RESURF diode using the SIPOS layer have increased and saturated at $8{\mu}m$. And it has decreased with increasing the surface oxide thickness.