• 전자공학회논문지A
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• 제29A권11호
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• pp.97-106
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• 1992

In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.871-875
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• 1996

The Output feedback linear quadratic regulator control is applied to the design of active suspension system using 7 DOF full car model. The performance index reflects the vehicle vertical movement, pitch and roll motion, and minimization of suspension stroke displacements in the rattle space. The elements of gain matrix are approximately decoupled so that each suspension requires only local information to generate the control force. The simulation results indicates that the output feedback LQ controller is more effective than purely passive or full state feedback active LQ controllers in following the road profile at the low frequency range and suppressing the road disturbance at the high frequency ranges.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.181-187
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• 2003

This paper presents an 125MHz, 128-phase phase-locked loop using interpolation technique for digital timing recovery. To reduce the power consumption and chip area, phase interpolation was performed over only selected windows, instead of overall period. Four clocks were used for phase interpolation to avoid the output jitter increase due to the interpolation clock (clock used for phase interpolation) switching. Also, the output clock was fed back to finite-state machine (FSM) where the multiplexer selection signals are generated to eliminate the possible output glitches. The PLL implemented in a $0.25\mu\textrm{m}$ CMOS process and dissipates 80mW at 2.5V supply and occupies $0.84\textrm{mm}^2.

• Transactions on Electrical and Electronic Materials
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• 제7권3호
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• pp.103-107
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• 2006

In this paper, a CMOS complementary bridge rectifier for driving RFID transponder chips is presented. The proposed RFID CMOS complementary bridge rectifier is designed with two NMOSs at the input, which are configured by cross-connected gate structures, and two PMOSs and two NMOSs at the output, which are configured by diode-connected MOS structures. Output characteristics of the proposed rectifier are analyzed with the high frequency small-signal equivalent circuit and verified with SPICE for RFID operating frequencies of 13.56 MHz HF for ISO 18000-3, 915MHz UHF for ISO 18000-6, and 2.45 GHz microwave for ISO 18000-4. Simulation results show well-rectified and high enough DC output voltages for driving the low power microchip in the RFID transponder for the frequency range from HF to microwave. DC output voltages are dropped by only around 0.7 V from the input peak-to-peak voltages.

• Advances in Energy Research
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• 제5권4호
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• pp.321-339
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• 2017

Energy simulation tools can provide information on the amount of heat transfer through building envelope components, which are considered the main sources of heat loss in buildings. Therefore, it is important to improve the quality of outputs from energy simulation tools and also the process of obtaining them. In this paper, a new Building Energy Performance Assessment Tool (BEPAT) is introduced, which provides users with granular data related to heat transfer through every single wall, window, door, roof, and floor in a building and automatically saves all the related data in text files. This information can be used to identify the envelope components for thermal improvement through energy retrofit or during the design phase. The generated data can also be adopted in the design of energy smart homes, building design tools, and energy retrofit tools as a supplementary dataset. BEPAT is developed by modifying EnergyPlus source code as the energy simulation engine using C++, which only requires Input Data File (IDF) and weather file to perform the energy simulation and automatically provide detailed output. To validate the BEPAT results, a computer model is developed in Revit for use in BEPAT. Validating BEPAT's output with EnergyPlus "advanced output" shows a difference of less than 2% and thus establishing the capability of this tool to facilitate the provision of detailed output on the quantity of heat transfer through walls, fenestrations, roofs, and floors.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2019년도 춘계학술대회
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• pp.389-391
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• 2019

본 연구에서는 유무선 전화기를 이용하여 원격지에 안내방송을 출력할 수 있는 원격방송시스템을 설계하였다. 설계된 원격방송시스템은 LTE 모듈을 이용하여 무선으로 수신된 전화 음성을 앰프를 통하여 증폭하여 출력하도록 하였다. 또한 문자메시지 전송이 가능한 유무선 전화기를 통해 원격방송시스템에 방송용 문자메시지를 보낼 수 있으며 이를 수신한 원격방송시스템은 음성장치 안에 저장된 해당 안내방송을 자동으로 출력할 수 있도록 구현하였다. 보안을 위하여 관리자 및 등록된 사용자만 시스템을 사용할 수 있도록 수신자의 전화번호를 비교 알고리즘을 통하여 분석하도록 하였다. 이 때 등록된 사용자로 확인된 경우에만 녹음된 안내 방송을 스피커를 통하여 출력하게 된다. 이 연구에서 설계된 시스템을 통하여 사용자는 시간과 장소의 제한을 받지 않고 신속하게 안내방송을 출력할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.36-42
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• 2007

A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.2043-2050
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• 2017

This paper presents two MPC (Model Predictive Control) based charging and discharging algorithms of BESS (Battery Energy Storage System) for capacity firming of wind generation. To deal with the intermittency of the output of wind generation, a single BESS is employed. The proposed algorithms not only make the output of combined systems of wind generation and BESS track the predefined reference, but also keep the SoC (State of Charge) of BESS within its physical limitation. Since the proposed algorithms are both presented in simple if-then statements which are the optimal solutions of related optimization problems, they are both easy to implement in a real-time system. Finally, simulations of the two strategies are done using a realistic wind farm library and a BESS model. The results on both simulations show that the proposed algorithms effectively achieve capacity firming while fulfilling all physical constraints.

• Journal of Communications and Networks
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• 제13권1호
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• pp.63-69
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• 2011

In this paper, we propose a fixed-complexity sphere encoder (FSE) for multi-user multi-input multi-output (MU-MIMO) systems. The proposed FSE accomplishes a scalable tradeoff between performance and complexity. Also, because it has a parallel tree-search structure, the proposed encoder can be easily pipelined, leading to a tremendous reduction in the precoding latency. The complexity of the proposed encoder is also analyzed, and we propose two techniques that reduce it. Simulation and analytical results demonstrate that in a $4{\times}4$ MU-MIMO system, the proposed FSE requires only 11.5% of the computational complexity needed by the conventional QR decomposition with M-algorithm encoder (QRDM-E). Also, the encoding throughput of the proposed encoder is 7.5 times that of the QRDM-E with tolerable degradation in the BER performance, while achieving the optimum diversity order.

• 한국통신학회논문지
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• 제25권6A호
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• pp.910-917
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• 2000

Because the random early detection(RED) algorithm deals all flows with the same best-effort traffic characteristic, it can not correctly control the output link bandwidth for the flows with different traffic characteristics. To remedy this problem, several per-flow algorithms have been proposed. In this paper, we propose a new per-flow type Fair Droptail algorithm which can fairly allocate bandwidth among flows over a shared output link. By evenly allocating buffers per flow, the Fair Droptail can restrict a flow not to use more bandwidth than others. In addition, it can be simply implemented even if it employs the per-flow state mechanism, because the Fair Droptail only keeps each information of flow in active state.