• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.5
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• pp.437-443
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• 2004

Aperture has been employed on the ground plane in the hairpin resonator. Aperture has been fabricated by etching the part of the ground effected coupling coefficient and then quality factor of hairpin resonator has been increased. When the hairpin oscillator using aperture has been compared with the conventional hairpin oscillator using microstrip, it has been improved the phase noise about 19 ㏈c @100 ㎑. As a result of PBG connecting to the output of the employing aperture hairpin oscillator, the second and third harmonics are suppressed. In this paper, oscillator has been designed and fabricated in operating 5.8 ㎓ band. The output power has been obtained 0,67 ㏈m and the second harmonic has been suppressed about -53,67 ㏈c.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1982-1990
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• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.9
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• pp.1010-1019
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• 2008

In this paper, we present a noise analysis and measurement results of a bio-radar system that can detect human heartbeat and respiration signals. The noise analysis including various phase noise effects is very important in designing the bio-radar system, since the frequency difference between the received signal and local oscillator is very small and the received power is very low. All of the noise components in a bio-radar system are considered from the point of view of SNR. From this analysis, it can be concluded that the phase noise due to antenna leakage is a dominant factor and is a function of range correlation. Therefore, the phase noise component with range correlation effect, which is the most important noise contribution, is measured using the measurement setup and compared with the calculated results. From the measurement results, our measurement setup can measure a closed-in phase noise of a free-running oscillator. Based on these results, it is possible to design a 2.4 GHz bio-radar system quantitatively which has a detection range of 50 cm and low power of 1 mW without additional PLL circuits.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.149-155
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• 2006

A technique used to induce maximum oscillating voltage in the BJT Clapp VCO is presented. The technique finds the optimal feedback capacitance values resulting in the largest oscillating signal swing across the resonator at a given bias state and the VCO's center frequency. By doing so, the presented technique attains the lowest phase noise which the BJT Clapp VCO can have. An analysis of the measurement results of the fabricated oscillators has verified that the VCO with the optimal feedback capacitance values actually exhibits the lowest phase noise.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.4
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• pp.622-629
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• 2001

An engineering model VCO with a good phase noise for Ku-band satellite transponder is designed using a nonlinear design methodology. It generates frequencies from 1,745 and 1,755 MHz with control voltages from 0 to 5 V DC. This unit requires 7 mA of current from 5 V DC supply voltage. Phase noise characteristics of the manufactured VCO exhibit -114 dBc/Hz @10 kHz offset and -131 dBc/Hz @100 kHz of offset and its output power is 5 dBm.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.941-944
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• 2015

In this paper study for VSAT(very small aperture terminal) LNB(low noise block). ship LNB was demanded high stability and low noise figure. We designed FEM(Front-End Module) that was operated multi-band. FEM designed was constructed in a multi-band low noise receiver amplifier, a frequency converter, IF amplifier, Voltage Control Oscillator signal generating circuit four circuit using. To convert the multi-band 2.05GHz band, it generates four local oscillator signals, the four(band1, band2, band3, band4) designed to output an IF signal developed conversion apparatus, the conversion gain 64dB, noise figure 1dB or less, output P1dB 15dBm or more, phase noise showed -73dBc@100Hz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.540-549
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• 2017

A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.3 no.2 s.5
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• pp.69-74
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• 2004

In this work, A PLDRO (Phase Locked Dielectric Resonator Oscillator) which can be used for the wireless communication systems fur MMC(Microwave Micro Cell) and ITS wireless communication system is designed. A different approach to the PLDRO structure is applied for phase locking by dual phase lock loop structure. The proposed dual loop PLDRO generates the output power of 0 dBm at 18.7 GHz and has the characteristics of a phase noise of -80 dBc/Hz at 1kHz, -83 dBc/Hz at 10 kHz offset frequency from carrier frequency