• 접착 및 계면
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• 제20권4호
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• pp.155-161
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• 2019

공액분자 나노구조체 계면에서의 전하이동 이방성을 이해하는 것은 유기전계효과트랜지스터(OFET)에서 구조-물성 상관관계를 규명하는데 중요하다. 본 연구에서는 대표적인 코페이셜 적층구조를 가진 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) 유기반도체 단결정과 산화물 계면에서 전하이동도 이방성을 연구하였다. 용매치환공정을 이용해 유기단결정을 산화실리콘 절연체 표면에 성장시키고 유기단결정/산화물 계면에서 전하이동을 유도할 수 있도록 OFET 소자를 완성하였다. TIPS-pentacene OFET에서 최고/최저 전하이동도 이방성은 5.2로 관찰되었다. TIPS-pentacene의 전하이동을 담당하는 공액부의 최인접부와의 상호작용을 분석한 결과, HOMO 준위 커플링과 전하의 호핑 궤도가 전하이동도 이방성에 기여하는 것으로 밝혀졌다. HOMO 준위 커플링에 기반한 전하이동도 이방성의 정량적 예측은 실험결과와 유사하게 나타났다.

• 지능정보연구
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• 제28권4호
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• pp.135-155
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• 2022

본 연구는 Organic Light-Emitting Diodes(OLEDs) 산업의 하위기술 분야를 도출하여 특허 동향을 분석하고 각 하위기술 분야별 기술 가치, 독창성, 다양성을 분석한다. 특허 자료 수집을 위해 OLED 기술과 관련된 국제 특허 분류(International Patent Classification) 집합을 정의하고, 이를 활용해 2005년부터 2017년까지 출원된 OLED 연관 특허를 수집하였다. 이어서 토픽모델을 이용하여 대량의 특허 문서를 12가지 주요 기술로 구분하고 각 기술에 대한 동향을 조사하였다. 그중 터치 센서, 모듈, 이미지 처리, 회로 구동 관련 특허는 증가 추세를 보였으나 가상 현실, 사용자 인터페이스 관련 특허는 최근 감소하였고, 박막 트랜지스터, 지문 인식, 광학필름 관련 특허는 지속적인 추세를 보였다. 이후 각 기술 그룹에 포함된 특허의 전방 인용 수, 독창성, 다양성을 조사하여 기술적 가치를 비교하였다. 결과로부터 전방 인용 수, 독창성, 다양성이 높은 이미지 처리기술, UI/UX, 모듈 기술, 점착 기술 분야가 상대적으로 높은 기술적 가치를 보여주었다. 본 연구를 통해 기업의 기술 전략 수립과정에서 활용 가치가 높은 정보를 제공한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.5-5
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• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.

• 한국진공학회지
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• 제17권5호
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• pp.435-441
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• 2008

본 논문은 TIPS Pentacene을 유기반도체로 사용한 유기박막 트랜지스터의 용제에 따른 전기적 특성에 대한 연구로서, 용제로는 chlorobenzene, p-xylene, chloroform, toluene을 사용하였으며, 회전 도포 방법을 사용하여 TIPS pentacene을 혼합하여 적층하였다. chlorobenzene을 사용하여 만들어진 유기박막 트랜지스터는 $1.0{\times}10^{-2}cm^2/V{\cdot}s$의 전계효과 이동도, $4.3{\times}10^3$의 on/off 비율, 5.5 V의 문턱전압의 특성을 보였다. 반대로, chloroform을 사용하여 만들어진 유기박막 트랜지스터는 $5.8{\times}10^{-7}cm^2/V{\cdot}s$의 전계효과 이동도, $1.1{\times}10^2$의 on/off 비율, 1.7 V의 문턱전압의 특성을 보였다. 또한 각 용제에 따른 TIPS pentacene 결정크기를 AFM을 통하여 측정하였다. 이와 같은 결과들을 통하여, 더 높은 끊는점을 가진 용제는 TIPS Pentacene의 더 큰 결정 크기와 높은 결정화 성향으로 인하여 더 좋은 전기적 특성을 가지는 것을 확인할 수 있었으며, 본 실험에서는 끓는점이 가장 높은 chlorobenzene을 사용한 TIPS Pentacene 유기박막 트랜지스터가 가장 좋은 전기적 특성을 나타내는 것을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.421-427
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• 2009

We successfully fabricated 4.7-inch organic thin film transistors array with $640{\times}480$ pixels on flexible substrate. All the processes were done by photolithography, spin coating and ink-jet printing. The OTFT-Electrophoretic (EP) pixel structure, based on a top gate OTFT, was fabricated. The mobility, ON/OFF ratio, subthreshold swing and threshold voltage of OTFT on flexible substrate are: 0.01 ^2/V-s, 1.3 V/dec, 10E5 and -3.5 V. After laminated the EP media on OTFT array, a panel of 4.7-inch $640{\times}480$ OTFT-EPD was fabricated. All of process temperature in OTFT-EPD is lower than $150^{\circ}C$. The pixel size in our panel is $150{\mu}m{\times}150{\mu}m$, and the aperture ratio is 50 %. The OTFT channel length and width is 20 um and 200um, respectively. We also used OTFT to drive EP media successfully. The operation voltages that are used on the gate bias are -30 V during the row data selection and the gate bias are 0 V during the row data hold time. The data voltages that are used on the source bias are -20 V, 0 V, and 20 V during display media operation.

• 한국전기전자재료학회논문지
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• 제24권1호
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• pp.12-16
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• 2011

In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to $90^{\circ}C$ and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; $O_2$ Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as $0.63cm^2 V^{-1}s^{-1}$, $1.7{\times}10^{-6}$, and of 0.75 V/decade, respectively.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• 산업경영시스템학회지
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• 제40권1호
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• pp.114-123
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• 2017

The global small and mid-sized display market is changing from thin film transistor-liquid crystal display to organic light emitting diode (OLED). Reflecting these market conditions, the domestic and overseas display panel industry is making great effort to innovate OLED technology and incease productivity. However, current OLED production technology has not been able to satisfy the quality requirement levels by customers, as the market demand for OLED is becoming more and more diversified. In addition, as OLED panel production technology levels to satisfy customers' requirement become higher, product quality problems are persistently generated in OLED deposition process. These problems not only decrease the production yield but also cause a second problem of deteriorating productivity. Based on these observations, in this study, we suggest TRIZ-based improvement of defects caused by glass pixel position deformation, which is one of quality deterioration problems in small and medium OLED deposition process. Specifically, we derive various factors affecting the glass pixel position shift by using cause and effect diagram and identify radical reasons by using XY-matrix. As a result, it is confirmed that glass heat distortion due to the high temperature of the OLED deposition process is the most influential factor in the glass pixel position shift. In order to solve the identified factors, we analyzed the cause and mechanism of glass thermal deformation. We suggest an efficient method to minimize glass thermal deformation by applying the improvement plan of facilities using contradiction matrix in TRIZ. We show that the suggested method can decrease the glass temperature change by about 23% through an experiment.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 추계종합학술대회
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• pp.758-760
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• 2007

최근에 유기물 전계효과 트랜지스터의 연구는 전자 소자 분야에서 널리 알려져 있다. 특히 본 연구에서는 CuPc 물질을 기본으로 하여 소자를 제작하고, 또한 기판의 온도를 달리 하여 CuPc/Au 구조 소자의 표면 전위 특성을 측정하였다. 기판은 slide glass를 사용하였고, CuPc 박막파 Au 전극은 진공 증착법을 이용하였다. 측정 온도의 범위는 0 - $100^{\circ}C$이었으며, 모든 측정은 진공 상태에서 측정이 이루어 졌다. 상온에서의 표면 전위 값은 약 600mV의 값을 보이고 있으며, 기판의 온도가 $100^{\circ}C$일 때 표면 전위 값은 약 500mV의 값으로 감소하는 것을 알 수 있다. 이러한 표면 전위 값의 변화는 기판의 온도가 상승하면서 CuPc 벌크 박막의 특성이 변화하는 것으로 판단되며, AFM 측정을 통해 확인 할 수 있었다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.61-63
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• 2005

Pentacene based OTFT on PC and PES plastic substrates have been fabricated in a scale of 5 inches. We could get a small OTFT device enough to be applicable for AMOLED by acquiring the at least misalignment margin through a contact aligner. And also we could find out the degradation of device parameter through the integration processes and improve the properties by using a buffer layer as an etch stopper in an active patterning. Through these, the mobility of device is more than about $0.2cm^2/Vs$ and $I_{on}/I_{off}$ is higher than $10^5$.