• Journal of KIISE:Computer Systems and Theory
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• v.29 no.3
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• pp.134-142
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• 2002

Quadtree, which is a hierarchical data structure, is a very important data structure to represent binary images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The window operation is one of important geometry operations in image processing, which extracts a sub-image indicated by a window in the image. In this paper, we present an algorithm to perform the window operation of binary images represented by quadtrees, using three-dimensional $n{\times}n{\times}n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to route the locational codes of quardtree on the hierarchical structure of $n{\times}n{\times}n$ RMESH.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.315-324
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• 2017

The smart grid with distributed power supply introduces a number of problems including not only the problems of the existing power grid but also the problem of protection co-operation due to new electric phenomenon because it has a mixed operation structure combining the existing radial operation structure and the new loop operation structure. The EMTP based power system analysis method has flexibility and convenience from the view of system configuration but it requires another experimental verification because of uncertainty of design and analysis results. On the other hand, the real demonstration system has difficulties in observing accurate fault on large scale system due to considerable economical and spatial construction cost, system configuration constraint, and it is difficult to demonstrate the distributed, autonomous and adaptive control strategy of smart grid. In this paper, a basic theory for a micro smart grid simulator design using MEMS(Micro Electro-Mechanical Systems) miniaturization technology is studied which can safely and freely experiment and observe electrical phenomena, and distribution, autonomous adaptive control strategy for disturbances on 22.9kV smart grid under minimum economic and spatial cost.

• Journal of the Korean Society of Safety
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• v.36 no.5
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• pp.79-85
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• 2021

A standard engineering model that reflects the current organization system and engineering operation process of domestic nuclear power plants was developed based on the Standard Nuclear Performance Model developed by the American Nuclear Energy Association. The level 0 screen, which is the main screen of the engineering model computer system, consisted of an object tree structure, which provided information that is phased down from a higher structure level to a lower structure level (i.e., level 3). The level 1 screen provided information related to the sub-process of the engineering operation, whereas the Level 2 screen provided information related to each engineering operation activity. In addition, the Level 2 screen provided additional functions, such as linking electronic procedures/guidelines, providing electronic performance forms, and connecting legacy computer systems (such as total equipment reliability monitoring system, configuration management systems, technical information systems, risk monitoring systems, regulatory information, and electronic drawing system). This screen level increased the convenience of user's engineering tasks by implementing them. The computerization of an engineering model that connects the entire engineering tasks of an establishment enables the easy understanding of information related to the engineering process before and after the operation, and builds a foundation for the enhancement of the work efficiency and employee capacity. In addition, KHNP developed an online training module, which operates as an e-learning process, on the overview and utilization of a standard engineering model to expand the understanding of standard engineering models by plant employees and to secure competitiveness.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.169-176
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• 2017

This paper presents research on low-voltage microgrids to maintain a continuous power supply to critical loads on grid-connected islands in Korea. The low-voltage microgrids of this paper focused on that changes public office buildings into uninterrupted microgrids by autonomous operation. For this, a microgrid controller (MGC) and a power conditioning system (PCS) that allow a seamless transfer between grid-connected and grid-isolated operation are proposed. The proposed PCS operates with a silicon controlled rectifier (SCR) switch and employs a simple structure. It supplies power continuously without operators through a coordinated operation between MGC and PCS. In addition, proposed MG has a schedule operation for minimizing electricity charges and provides ancillary services that enable the utilization of resources according to the operation purpose of utility distribution networks. To demonstrate the uninterrupted low-voltage microgrid proposed in this study, a microgrid was implemented and tested in a public office building in Anjwa Island, Jeollanam-do in Korea. A seamless, autonomous operation history, despite system disturbances, was obtained through a long-term demonstration of operation. The results showed that the proposed microgrid technology can be used to achieve energy resilience in grid-connected island areas.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.1
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• pp.413-435
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• 2018

Although the accuracy of handwritten character recognition based on deep networks has been shown to be superior to that of the traditional method, the use of an overly deep network significantly increases time consumption during parameter training. For this reason, this paper took the training time and recognition accuracy into consideration and proposed a novel handwritten character recognition algorithm with newly designed network structure, which is based on an extended nonlinear kernel residual network. This network is a non-extremely deep network, and its main design is as follows:(1) Design of an unsupervised apriori algorithm for intra-class clustering, making the subsequent network training more pertinent; (2) presentation of an intermediate convolution model with a pre-processed width level of 2;(3) presentation of a composite residual structure that designs a multi-level quick link; and (4) addition of a Dropout layer after the parameter optimization. The algorithm shows superior results on MNIST and SVHN dataset, which are two character benchmark recognition datasets, and achieves better recognition accuracy and higher recognition efficiency than other deep structures with the same number of layers.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.31-37
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• 1997

This paper describes the design and implementation of 8 bit ALU graphic simulator which helps students who study the structure and operation course of general ALU. ALU of this paper consists of three parts, arithmetic circuit, logic circuit, and shifter. Each of them performs as follows. Arithmetic circuit performs arithmetic operation such as addition, subtraction, 1 increment, 1 decrement, 2's complement, logic circuit performs logic operation such as OR, AND, XOR, NOT, and shifter performs shift operation and transfers the result of circuits of arithmetic, logic to data bus. The instructions which relate to these basic ALU functions was selected from Z80 instructions and ALU circuit was designed with those instructions and this designed ALU circuit was implemented on graphic screen. And all state of this data operation course in ALU was showed by bit and logic gate unit.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1249-1254
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• 2010

The bogie structure of center guided type monorail has been applied to Incheon Wolmi Eunha monorail at first in the world, and aluminum alloy material bogie is first ever introduced in Korea. Since bogie transfers vertical and horizontal loads to the track and guide rail as an essential system, its structure should have enough durability and secure excellent operation performance and ride quality. This study presents a suitable structure for center guided type monorail, a system combination method for bogie operation performance and riding quality, and a solution for better bogie frame durability.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.8
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• pp.718-729
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• 2015

A S / X dual broad band patch antenna with shared aperture structure is fabricated. A $2{\times}2$ perforated patch is used for S-band operation and a $2{\times}2$ patch antenna array is integrated in the $2{\times}2$ perforation for X-band operation. The measurement results of a S / X dual broad band patch antenna with shared aperture structure show the broad band characteristics larger than 20 % in both bands.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.528-535
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• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1345-1359
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• 1996

This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.