• 전자공학회논문지
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• 제49권9호
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• pp.259-269
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• 2012

전원 전압이 낮아지고, 칩의 동작 속도가 빨라짐에 따라 온-칩 인덕턴스를 포함한 power distribution network (PDN) 분석이 중요해 질 것으로 예측된다. 본 논문에서는 일반적인 온-칩 전력 격자 구조에 적용시킬 수 있는 효과적인 인덕턴스 추출방법에 대해 제안한다. Chip layout에 적용할 수 있는 loop 인덕턴스 모델을 제시하고, 그 모델을 사용하여 post layout RC extraction netlist로 부터 인덕턴스를 포함한 netlist를 추출할 수 있는 tool을 개발하였다. 제안된 loop 인덕턴스 모델과 개발된 tool의 정확성은 회로 simulation을 통해 PEEC 모델과 비교하여 검증하였다. 인덕턴스 추출 방법을 실제 chip layout에 적용시켜 on-chip inductance를 포함한 PDN의 voltage fluctuation을 예측하였다. 패키지와 PCB 모델을 포함한 co-simulation 모델을 구성하여 on-chip inductance의 영향을 분석하였다.

• Nuclear Engineering and Technology
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• 제53권10호
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.