• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.139.4-139
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• 1998

• Journal of the Semiconductor & Display Technology
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• v.3 no.3
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• pp.31-35
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• 2004

A blue light emitting diode with 8 periods InGaN/GaN multi-quantum well structure grown by metal-organic chemical vapor deposition was fabricated with the inclusion of the metal-interconnection process in order to integrate the chips for light lamp. The quantum well structure provides the blue light photoluminescence peaked at 479.2 nm at room temperature. As decreasing the temperature to 20 K, the main peak was shifted to 469.7 nm and a minor peak at 441.9 nm appeared indicating the quantum dot formation in quantum wells. The current-voltage measurement for the fabricated LED chips shows that the metal-interconnection provides good current path with ohmic resistance of 41 $\Omega$.

• Journal of IKEEE
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• v.17 no.2
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• pp.176-181
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• 2013

This paper presents a CMOS impulse radio ultra-wideband (IR-UWB) receiver implemented using IBM 0.13um CMOS technology for inner/inter-chip wireless interconnection. The IR-UWB receiver is based on the non-coherent architecture which removes the complexity of RF architecture (such as DLL or PLL) and reduces power consumption. The receiver consists of three blocks: a low noise amplifier (LNA) with active balun, a correlator, and a comparator. Simulation results show the die area of the IR-UWB receiver of 0.2mm2, a power gain (S21) of 12.5dB, a noise figure (NF) of 3.05dB, an input return loss (S11) of less than -16.5dB, a conversion gain of 18dB, a NFDSB of 22. The receiver exhibits a third order intercept point (IIP3) of -1.3dBm and consumes 22.9mW of power on the 1.4V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.40-49
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• 2011

Integrating massive components and low-power policies have been actively investigated for system-on-chip designs. But in recent years, finding the optimal interconnection structure among heterogeneous components has emerged as a critical system design issue. Therefore, various simulation tools to model interconnection designs are being developed and performance evaluation of simulation is reflected in the real design. But most of the simulation environments employ traffic generation based on the mathematical probability functions, and such traffic generation cannot fully cover for various situations that may be occurred in the real system. Therefore, the demand for traffic pattern generation based on real applications is increasing. However, there have been few simulators that adopt application-specific traffic generators. This paper proposes a novel traffic generation method in simulating various interconnection structures for multi-processor system-on-chip design. The proposed traffic generation method can generate traffic patterns that can reflect the actual characteristics of the application and evaluate the performance of an interconnection structure under more realistic circumstance than traffic patterns using mathematical probability functions. By comparing the differences between the proposed method and the one based on mathematical probability functions, this paper shows advantages of the proposed traffic generation method.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.45-46
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• 2011

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.114-120
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• 1995

It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of mutiple interconnect faults.

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.185-192
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• 1989

It is shown that GaAs/GaAs stripe Roof-Top-Reflector LD is better than cleaved mirror LD by numerical analysis. And surface light emitting device is developed by LPE melt-back growth, which is of good controllability for OEIC. OEIC transmitter using RTR LD structured device and FET has been made and modulated, expected to show good modulation characteristics after solving process problem. Beam-Lead LD mounted on Si carrier has been made and shows low heat-resistance and so long life and good characteristics of LD.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.29-36
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• 2004

A flexible packaging scheme, which includes chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending tests and finite element analysis. Thinned silicon chips (t<30 $\mu\textrm{m}$) are fabricated by chemical etching process to avoid possible surface damages on them. And the chips are stacked directly on $Kapton^{Kapton}$film by thermal compressive bonding. The low height difference between the thinned silicon chip and $Kapton^{Kapton}$film allows electroplating for electrical interconnection method. Because the 'Chip' is embedded in the flexible substrate, higher packaging density and wearability can be achieved by maximized usable packaging area.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.95-99
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• 2001

Cu is considered as a promising alternative interconnection material to Al-based interconnection materials in Si-based integrated circuits due to its low resistivity and superior resistance to the electromigration. New humping and UBM material systems for solder flip chip interconnection of Cu pads were investigated using electroless-plated copper (E-Cu) and electroless-plated nickel (E-Ni) plating methods as low cost alternatives. Optimally designed E-Ni/E-Cu UBM bilayer material system can be used not only as UBMs for solder bumps but also as bump itself. Electroless-plated E-Ni/E-Cu bumps assembled using anisotropic conductive adhesives on an organic substrate is successfully demonstrated and characterized in this study

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.89-90
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• 2000

A new technology realizing interconnection between Plastic Film LCDs panel and a driving circuit was developed under the processing condition of low temperature and pressure with ACFs developed for Plastic Film LCDs. The conduction failure of interconnection of the two resulted from elasticity, low thermal resistance and high thermal expansion of plastic substrates. Conductive particles with elasticity similar to the plastic substrate did not damaged a ITO electrode on plastic substrates, and low temperature and pressure process also did not deform the surface of plastic substrates. As a result highly reliable interconnection with minimum contact resistance was accomplished.