• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.259-269
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• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

• Journal of the Semiconductor & Display Technology
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• v.14 no.3
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.12
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• pp.2926-2935
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• 1993

Chip breaker selection analysis, only being possible through experimental process, was obtained by a applied equation which used an orthogonal cutting model and a basic chip deformation. This equation could present an analysis of the chip breaking phenomena without the use of an actual experimetal method, and it was applied to computer simulation and proved the validity of theory through actual experiments. From these results, an efficient method for finding the optimum conditions of chip breaking was found through an optimized theory being applied to basic program. A finite element model for simulating chip breaking in orthogonal cutting was developed and discussed. By simulation the animation of chip breaking is observed in process on the computer screen.

• Journal of the Korean Society of Safety
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• v.9 no.4
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• pp.17-28
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• 1994

Chip breaking is important in lathe work for maintaining good surface of the products and safety of operator. The purpose of this study is to investigate the performance of chip breaking and chip shape resulted from the carbide inserts with grooved type and obstruction type chip breaker. Experiments have been performed under the following cutting conditions, (1) constant cutting speed with variable depth of cut and feed rate, (2) constant depth of cut with variable cutting speed and feed rate. Also, the flying distance of chip and it's distribution have been investigated. As a results, good performance of chip breaking can be obtained for small radius of curvature and land width of grooved type chip breaker. And the thickness of chip increase with the increase of feed rate and decrease of cutting speed, and the chip breaking becomes easier with the increase of chip thickness due to the large deformation rate. Obstraction type chip breaker shows better performance of surface roughness than the grooved type. The flying distance of the chips over 90% are less than 1 meter, and the distance decreases as the feed rate decreases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.9 no.3
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• pp.48-54
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• 2000

In this study the characteristics of chip formation of the cold drawn Bi-S free machining steels were assessed. And for comparison those of the cold drawn Pb-S free machining steel the hot rolled low carbon steel which has MnS as free machining inclusions and the conventional steels were also investigated. During chip formation the cold drawn free machining steels show relatively little change in thickness and width of chip compare to those of the conventional carbon steels. And a single parameter which indicates the degree of deformation during chip formation chip cross-section area ratio is introduced. The chip cross-section area ratio is defined as chip cross-section area is divided by undeformed chip cross-section area. The variational patters of the chip cross-section area ratio of the materials cut are similar to those of the shear strain values. The shear stress however seems to be dependent on the carbon content of the materials. The cold drawn Bi-S and Pb-S steels show nearly the same chip forming behaviors and the energy consumed during chip formation is almost same. A low carbon steel without free machining aids shows poor chip breakability due to its high ductility. By introducing a small amount of free machining inclusions such as MnS Bi, Pb or merely increasing carbon content the chip breakability improves significantly.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.271-275
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• 1995

Chip control is a major problem in automatic machining process, especially in finish operation. Chip breaker is one of the important factors to be determined for the scheme of chip control. As unbroken chips are grown, there deteriorate quality of the surface roughness and process automation can be carried out. In this study, to get rid of chip curling problem while turning internal hole, optimal chip breaker is selected form the experiment. The experiment is planned with Taguchi's method that is based on the orthogonal arrary of design factor. From the respose table, cutting speed, feedrate, depth of cut, and tool geometry are major factors affecting chip formation. Then, optmal chip breaker is selected and this is verified good enough for chip control from the experiment.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.10a
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• pp.351-356
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• 1999

In this study, the characteristics of chip formation of the cold drawn Bi-S free machining steels were assessed. And for comparison, those of the cold drawn Pb-S free machining steel, the hot rolled low carbon steel which has MnS as free machining inclusions and the conventional steels were also investigated. During chip formation, the cold drawn free machining steels show relatively little change in thickness and width of chip compare to those of the conventional carbon steels. And a single parameter which indicates the degree of deformation during chip formation, 'chip cross-section area ratio' is introduced. The chip cross-section area. The variational patterns of cross-section area is divided by undeformed chip cross-section area. The variational patterns of the chip cross-section area ratio of the materials cut are similar to those of the shear strain values. The shear stress, however, seems to be dependent on the carbon content of the materials. The cold drawn BiS and Pb-S steels show nearly the same chip forming behaviors and the energy consumed during chip formation is almost same. A low carbon steel without free machining aids shows poor chip breakability due to its high ductility. By introducing a small amount of non-metallic inclusions such as MnS, Bi, Pb or merely increasing carbon content the chip breakability improves significantly.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1120-1127
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• 2013

In this paper, novel chip-on-chip(CoC) flip-chip bump structures using chip-on-wafer(CoW) process technology are proposed, designed and fabricated, and their microwave frequency responses are analyzed. With conventional bumps of Cu pillar/SnAg and Cu pillar/Ni/SnAg and novel Polybenzoxazole(PBO)-passivated bumps of Cu pillar/SnAg, Cu pillar/Ni/SnAg and SnAg with the deposition option of $2^{nd}$ Polyimide(PI2) layer on the wafer, 10 kinds of CoC samples are designed and their frequency responses up to 20 GHz are investigated. The measurement results show that the bumps on the wafers with PI2 layers are better for the batch flip-chip process and have average insertion loss of 0.14 dB at 18 GHz. The developed bump structures for chips with fine-pitch pads show similar or slightly better insertion loss of 0.11~0.14 dB up to 18 GHz, compared with that of 0.13~0.17 dB of conventional bump structures in this study, and we find that they could be utilized in various microwave packages for high integration density.