• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.10A
• /
• pp.922-929
• /
• 2005

This paper proposes an adaptive pilot beacon equipment for mobile communication systems based on direct spread spectrum technology which generates the pilot channel for handoff between base stations by using the information acquired from the downstream wireless signal regarding the overhead channel information. Such an adaptive pilot beacon equipment will enable low power operation since among the wireless signals, only the pilot channel will be generated and transmitted. The pilot channel in the downstream link of the CDMA receiver is used to acquire time and frequency synchronization and this is used to calibrate the offset for the beacon, which implies that time synchronization using GPS is not required and any location where forward receive signal can be received can be used as the installation site. The downstream link pilot signal searching within the CDMA receiver is performed by FPGA and DSP. The FPGA is used to perform the initial synchronization for the pilot searcher and DSP is used to perform the offset correction between beacon clock and base station clock. The CDMA transmitter the adaptive pilot beacon equipment will use the timing offset information in the pilot channel acquired from the CDMA receiver and generate the downstream link pilot signal synchronized to the base station. The intermediate frequency signal is passed through the FIR filter and subsequently upconverted and amplified before being radiated through the antenna.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.7
• /
• pp.635-645
• /
• 2016

In this paper, we showed the phase noise of voltage controlled oscillator(VCO) can be radically improved using FLL(Frequency Locked Loop). At first, a 5 GHz VCO is fabricated using a hair-pin resonator. The fabricated VCO shows a phase noise of -53.1 dBc/Hz at 1 kHz frequency offset. In order to improve the phase noise of the fabricated VCO, a FLL is constructed using the feedback loop that consists of the VCO, a frequency detector composed of 5 GHz resonator, loop-filter, and level shifter. The fabricated FLL is designed to oscillate at a frequency of 5 GHz, and its measured phase noise is about -120.6 dBc/Hz at 1 kHz offset frequency. As a result, the phase noise of VCO can be radically improved by about 67.5 dB applying FLL. In addition, the measured phase noise performance is close to that of crystal oscillator.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.769-772
• /
• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
• /
• v.1 no.1
• /
• pp.73-79
• /
• 2003

In a pressurized water reactor, radioactive corrosion products (CRUD) in primary coolant system are one of the major sources for the occupational radiation exposure of the personnel in a nuclear power plant. Through the recent trend of long term fuel cycle in a nuclear power Plant, radioactive corrosion products deposited in reactor core for a long time are also the cause of Axial Offset Anomaly (AOA) having m effect on reactor power by the hideout of boron. CRUD consist primarily of magnetite, nickel ferrite, cobalt ferrite, and so on. They have the characteristic of strong magnetism. Therefore it is performed the conceptual design to develop the filter which removes the CRUD by magnetic field that is generated by an arrangement of permanent and electric magnets. Contrary to the conventional filter, the proposed filter does not interrupt the fluid flow, so there is little pressure drop and it can be used continuously. It is expected to be applied as one of the technologies for removal of the CRUB.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.2A
• /
• pp.51-60
• /
• 2005

In this paper, we propose an enhanced SIR measurement algorithm for WCDMA mobile station modem. The proposed algorithm minimizes processing delay by applying velocity estimation-based channel estimator with IIR filter and reduces measured SIR offset by compensating attenuated signal power by using pilot channel(CPICH) in fading channel environment. To improve stability of SIR measurement, we also adopt an IIR filter which can properly reflect variation of fading channel in signal and interference power measurement. We prove that the proposed algorithm outperforms conventional SIR measurement algorithm in mean and jitter of measured SIR. Computer simulation shows that performance results using the proposed algorithm have improvement of approximately 8dB for measured mean and 2dB for measured jitter in the wireless mobile channel, especially in fast mobile speed environment.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2016.06a
• /
• pp.237-239
• /
• 2016

본 논문에서는 HEVC (High Efficiency Video Coding) 복호화기의 SAO (Sample Adaptive Offset)를 효율적으로 병렬화하기 위한 방법을 제안한다. HEVC 는 주관적 화질 향상 및 압축 효율 향상을 위해 디블록킹 필터 (de-blocking filter)와 샘플 적응적 오프셋 (SAO)이라는 두 가지 인-루프 필터를 사용한다. 두 종류의 인-루프 필터의 사용은 HEVC 복호화기의 복잡도를 증가시키는 요인이며, 인-루프 필터에 데이터레벨 병렬화를 적용하여 고속으로 복호화를 수행할 수 있다. 본 논문에서는 SAO 의 병렬화를 위해 CTU (Coding Tree Unit)의 행 단위로 병렬화를 수행함으로써, 병렬화로 인한 추가적으로 발생하는 라인 버퍼 사용을 줄여 SAO 병렬화 효율을 향상시켰다. 실험결과 제안하는 SAO 병렬화 방법을 사용하여 균등분할 SAO 병렬화 방법에 비해 91%의 속도를 향상시켰다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2016.06a
• /
• pp.369-372
• /
• 2016

본 논문에서는 고효율 비디오 부호화에서 채택하고 있는 인-루프 필터 중 SAO (sample adaptive offset)를 컨볼루션 신경망으로 대체하여 부호화 효율을 향상시키는 방법을 제안한다. SAO 는 양자화 에러를 줄이기 위해 인코더에서 디코더로 적절한 오프셋 값을 전송한다. 제안하는 컨볼루션 신경망을 사용한 인-루프 필터는 인코더와 디코더가 같은 컨볼루션 신경망을 사용하여, 추가적인 비트를 디코더로 전송할 필요 없이 양자화 에러를 줄일 수 있다. 컨볼루션 신경망의 구조는 두 가지를 각각 사용하였고, 각 컨볼루션 신경망의 구조에 대해서 입력 영상과 원래 영상의 평균제곱오차에 따라 다른 모델을 적용하였다. 따라서 제안하는 방법을 HEVC에 적용하여 기존의 방법보다 더 적은 bit 로 더 좋은 화질의 영상을 얻어서 BD-rate 의 gain 을 얻을 수 있을 뿐만 아니라, 주관적인 화질의 비교에서도 더 좋은 결과를 보인다.

• Journal of Electrical Engineering and Technology
• /
• v.12 no.6
• /
• pp.2317-2323
• /
• 2017

Recently, linear compressors of cooling systems such as refrigerators, which have a free piston driven by a linear motor, have attracted much attention because of their high efficiency. For structural reasons, linear compressors applied in refrigerators should use an AC capacitor to ensure stable control. However, AC capacitors are expensive and bulky. In this paper, we propose a new method to realize stable control without a real AC capacitor by implementing a virtual AC capacitor with software. To realize a virtual AC capacitor, a pure integral is calculated. Nonetheless, if an offset current exists, the calculation may diverge to infinity. To solve this problem, a high-pass filter is applied and the compensation for the phase angle and magnitude are realized with a new method. Finally, a virtual AC capacitor enables variable frequency operations. Hence, in case of a lack of voltage, we can compensate by running the linear compressor in high-frequency operations. To improve efficiency, we may optimize the operation frequency. The validity of a virtual AC capacitor has been verified through simulations and experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.7
• /
• pp.1219-1225
• /
• 2001

In this Paper we describe the design of synchronization algorithms for burst QPSK receiver, which are applicable to BWLL uplink. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we ufo Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.313-321
• /
• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.