• 정보처리학회논문지C
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• 제14C권2호
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• pp.185-190
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• 2007

무선 센서 네트워크의 각 센서 노드는 배터리 기반의 제한된 에너지로 동작하기 때문에 무선 센서 네트워크에서의 효율적인 에너지 사용에 많은 연구가 이루어지고 있다. 무선 센서 네트워크의 수명을 연장하기 위해서는 무선 센서 네트워크에 존재하는 각 센서 노드들의 전력소비를 줄이는 것도 필요하지만 센서 노드들의 균일한 에너지 소비를 유도하여 가능한 많은 노드들이 생존하는 것이 망의 수명에 더욱 중요한 요인이 된다. 본 논문에서는 클러스터링 기반 라우팅 프로토콜인 LEACH를 기반으로 각 노드의 잔이 에너지를 고려하여 전체 노드의 균형적인 에너지 소모를 유도하는 클러스터 헤드 선정 알고리즘을 제안한다. 제안한 프로토콜에 대해서 시뮬레이션을 기반으로 네트워크 수명에 대한 분석을 수행하였다. 제안한 프로토콜은 심각한 오버헤드나 성능저하 없이 효과적으로 네트워크 수명을 연장하였다.

• 한국산업정보학회논문지
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• 제19권2호
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• pp.1-13
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• 2014

In IEEE 802.11p/1609-based vehicular networks, vehicles are allowed to exchange safety and control messages only within time periods, called control channel (CCH) interval, which are scheduled periodically. Currently, the length of the CCH interval is set to the fixed value (i.e. 50ms). However, the fixed-length intervals cannot be effective for dynamically changing traffic load. Hence, some protocols have been recently proposed to support variable-length CCH intervals in order to improve channel utilization. In existing protocols, the CCH interval is subdivided into safety and non-safety intervals, and the length of each interval is dynamically adjusted to accommodate the estimated traffic load. However, they do not consider the presence of hidden nodes. Consequently, messages transmitted in each interval are likely to overlap with simultaneous transmissions (i.e. interference) from hidden nodes. Particularly, life-critical safety messages which are exchanged within the safety interval can be unreliably delivered due to such interference, which deteriorates QoS of safety applications such as cooperative collision warning. In this paper, we therefore propose a new interference-aware Dynamic Safety Interval (DSI) protocol. DSI calculates the number of vehicles sharing the channel with the consideration of hidden nodes. The safety interval is derived based on the measured number of vehicles. From simulation study using the ns-2, we verified that DSI outperforms the existing protocols in terms of various metrics such as broadcast delivery ration, collision probability and safety message delay.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권8호
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• pp.2796-2813
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• 2014

This paper presents a new algorithm called the adaptive logarithmic increase and adaptive decrease algorithm (A-LIAD), which mainly addresses the Round-Trip Time (RTT) fairness problem in satellite networks with a very high propagation delay as an alternative to the current TCP congestion control algorithm. We defined a new increasing function in the fashion of a logarithm depending on the increasing factor ${\alpha}$, which is different from the other logarithmic increase algorithm adopting a fixed value of ${\alpha}$ = 2 leading to a binary increase. In A-LIAD, the ${\alpha}$ value is derived in the RTT function through the analysis. With the modification of the increasing function applied for the congestion avoidance phase, a hybrid scheme is also presented for the slow start phase. From this hybrid scheme, we can avoid an overshooting problem during a slow start phase even without a SACK option. To verify the feasibility of the algorithm for deployment in a high-speed and long-distance network, several aspects are evaluated through an NS-2 simulation. We performed simulations for intra- and interfairness as well as utilization in different conditions of varying RTT, bandwidth, and PER. From these simulations, we showed that although A-LIAD is not the best in all aspects, it provides a competitive performance in almost all aspects, especially in the start-up and packet loss impact, and thus can be an alternative TCP congestion control algorithm for high BDP networks including a satellite network.

• Journal of Magnetics
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• 제15권3호
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• pp.103-107
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• 2010

We investigated spin-polarized current switching of Pac-man type II (PM-II) nanoelements in Pac-man shaped nanoscale spin-valves (Co/Cu/Py) using micromagnetic simulations. The effects of slot angle and antiferromagnetic (AFM) layer were simulated to obtain optimum switching in less than 2 ns. At a critical slot angle of $105^{\circ}$, the lowest current density for anti-parallel to parallel (AP-P) switching was observed due to no vortex or antivortex formation during the magnetic reversal process. All other slot angles for AP-P formed a vortex or antivortex during the magnetization reversal process. Additionally, a vortex or anti-vortex formed for all slot angles for parallel to anti-parallel (P-AP) switching. The addition of an AFM layer caused the current density to decrease significantly for AP-P and P-AP at slot angles less than $90^{\circ}$. However, at slot angles greater than $90^{\circ}$, the current density tended to decrease by less amounts or actually increased slightly as shape anisotropy became more dominant. This allowed ultra-fast switching with 5.05 and $5.65{\times}10^8\;A/cm^2$ current densities for AP-P and P-AP, respectively, at a slot angle of $105^{\circ}$.

• 천문학회보
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• 제42권2호
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• pp.53.1-53.1
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• 2017

Gravitational wave (GW) is a probe to observe compact objects (WD, NS, and BHs) in the Universe. Compact binary coalescences (CBCs) were expected to be primary sources of LIGO, VIRGO, and KAGRA. Indeed GW150914 from BH-BH binary coalescence at 430 Mpc was discovered by LIGO between 25-350 Hz. The total system mass of GW150914 is ${\sim}70M_{\odot}$, and about $3M_{\odot}$ of energy is converted to GWs in 0.2s of the observation duration. In lower frequencies below 10 Hz, in addition to CBCs with $1-100M_{\odot}$, more massive sources of ${\sim}1,000-10,000M_{\odot}$ are observable for seconds up to days in time scale. We introduce GW astrophysics and present highlights of target sources for the proposed super conducting low-frequency gravitational-wave telescope (SLGT).

• International Journal of Aeronautical and Space Sciences
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• 제17권2호
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• pp.260-267
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• 2016

The design process of blended inlet body (BIB) for the preliminary design of a near-space high supersonic unmanned aerial vehicle (HSUAV) is presented. The mass flow rate and cowl area of inlet at a design point are obtained according to the cruise condition of the HSUAV. A mixed-compression axisymmetric supersonic inlet section with a fixed geometry reasonably matching the high supersonic cruise state is created by using the inviscid theory of aerodynamics. The inlet section is optimized and used as a baseline section for the BIB design. Three BIB concepts for the HSUAV are proposed, and their internal aerodynamic characteristics of inlet are evaluated using Euler computational fluid dynamics (Euler CFD) solver. The preferred concept is identified, in which the straight leading edge of the baseline HSUAV configuration is modified into the convex leading edge to accommodate the inlet and meet the requirements of the cowl area to capture the sufficient air flow. The total recovery of inlet for the preferred BIB concept and the aerodynamic characteristics of the modified HSUAV configuration are verified using Navier-Stokes computational fluid dynamics (NS CFD) solver. The validation indicates that the preferred BIB concept can meet both the requirements of the inlet and aerodynamic performance of the HSUAV.

• 대한전자공학회논문지
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• 제25권9호
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• 한국통신학회논문지
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• 제29권1B호
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• pp.86-100
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• 2004

To provide the end-to-end service differentiation for assured services, the random early demotion and promotion (REDP) marker in the edge router at each domain boundary monitors the aggregate flow of the incoming in-profile packets and demotes in-profile packets or promotes the previously demoted in-profile packets at the aggregate flow level according to the negotiated interdomain service level agreement (SLA). The REDP marker achieves UDP fairness in demoting and promoting packets through random and early marking decisions on packets. But, TCP fairness of the REDP marker is not obvious as for UDP sources. In this paper, to improve TCP fairness of the REDP marker, we propose a modified REDP marker where we combine a dropper, meters and a token filling rate configuration component with the REDP marker. To make packet transmission rates of TCP flows more fair, at the aggregate flow level the combined dropper drops incoming excessive in-profile packets randomly with a constant probability when the token level in the leaky bucket stays in demotion region without incoming demoted in-profile packets. Considering the case where the token level cannot stay in demotion region without the prior demotion, we propose a token filling rate configuration method using traffic meters. By using the token filling rate configuration method, the modified REDP marker newly configures a token filling rate which is less than the negotiated rate determined by interdomain SLA and larger than the current input aggregate in-profile traffic rate. Then, with the newly configured token filling rate, the token level in the modified REDP marker can stay in demotion region pertinently fir the operation of the dropper to improve TCP fairness. We experiment with the modified REDP marker using ns2 simulator fur TCP sources at the general case where the token level cannot stay in demotion region without the prior demotion at the negotiated rate set as the bottleneck link bandwidth. The simulation results demonstrate that through the combined dropper with the newly configured token filling rate, the modified REDP marker also increases both aggregate in-profile throughput and link utilization in addition to TCP fairness improvement compared to the REDP marker.

• 정보처리학회논문지C
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• 제16C권6호
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• pp.707-716
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• 2009

무선 센서 네트워크는 무작위로 설치된 센서 노드가 스스로 네트워크를 형성하여 수집한 환경 정보를 전송하는 네트워크이다. 센서 노드는 매우 제한된 자원으로 동작하기 때문에 무선 센서 네트워크는 기존 네트워크에서 사용되는 기법을 적용하기 어렵다. 특히 제한된 에너지를 가지고 동작해야 하기 때문에 전송에 소모되는 에너지를 줄이기 위한 연구와 다양한 종류의 데이터를 효율적으로 전송하여 QoS를 향상시키기 위한 기법들이 연구되고 있다. 본 논문에서는 기존의 연구들이 가졌던 단점을 개선하기 위해 노드에서 소모되는 에너지의 분산과 QoS를 고려한 에이전트 기반의 프레임워크를 제안한다. 에이전트의 행동을 결정하는 정책을 유전자화 시켜 각각의 에이전트가 스스로 자신의 행동을 결정하여 동작할 수 있게 하면서 유전자 알고리즘을 통해 에이전트의 정책을 최적화 할 수 있도록 하였다. NS-2를 이용한 시뮬레이션 결과 기존의 기법에 비해 본 논문에서 제안한 기법이 노드에서 소모되는 에너지를 분산시켜 네트워크의 생존시간을 연장시키는 것을 확인할 수 있었다. 또한 긴급한 데이터의 전송 성공률을 27%, 긴급하지 않은 데이터의 전송 성공률도 14% 향상시켜 네트워크의 QoS를 향상시켰다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.