• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.255-255
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• 2009

In this work, nonvolatile nano-floating gate memory devices were fabricated with ZnO films and Al nanoparticles using the sputtering method on a glass substrate. Al nanoparticles acted as floating gate nodes in the devices. The fabricated device exhibits a threshold voltage shift of 1.7 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.210-210
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.131.2-131.2
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• 2009

• Journal of the Korean Society of Tobacco Science
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• v.5 no.2
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• pp.71-75
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• 1983

The relative proportion of the major smoke components in the nonvolatile phase from some varieties of tobacco, 1. e. flue- cured, burley, and aromatic tobacco, were determined. In flue- cured tobacco smoke, hydroquinone and glycerol we re exhibited higher concentrations than in the smoke from the other tobaccos. In aromatic tobacco smoke, the contents of non-volatile phase were present in lower concentrations.

• Proceedings of the Korean Ceranic Society Conference
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• 2000.10a
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• pp.145.1-145
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• 2000

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.126-126
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• 2008

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.09a
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• pp.137-141
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• 2005

Quantum dot(QD) 메모리용 silicon nano-particle을 corona 방전방법에 의해 상온에서 대량 발생하는 방법을 개발하였다. Silicon QD는 SiH4 가스를 코로나 방전 영역을 통과시켜 발생시켰으며, 코로나 전압은 2.75kV를 사용하였다. SiH4 몰농도 $0.33{\times}10^{-7}\;mol/l$ 일 경우 발생된 QD입자 크기는 약 10nm이며 기하학적 표준편차(geometric standard deviation)는 1.31이었다. 이 조건에서 nonvolatile quantum dot semiconductor memory (NVQDM)를 제작하였으며, 이렇게 제작된 NVQDM flat band voltage는 1.5 volt였다.

• Transactions on Electrical and Electronic Materials
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• v.15 no.5
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• pp.241-244
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• 2014

Charge trap flash memory capacitors incorporating $(HfO_2)_x(Al_2O_3)_{1-x}$ film, as the charge trapping layer, were fabricated. The effects of the charge trapping layer composition on the memory characteristics were investigated. It is found that the memory window and charge retention performance can be improved by adding Al atoms into pure $HfO_2$; further, the memory capacitor with a $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer exhibits optimized memory characteristics even at high temperatures. The results should be attributed to the large band offsets and minimum trap energy levels. Therefore, the $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer may be useful in future nonvolatile flash memory device application.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.108-109
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• 2012

This talk will begin with the demonstration of facile synthesis of silicon nanostructures using the magnesiothermic reduction on silica nanostructures prepared via self-assembly, which will be followed by the characterization results of their performance for energy storage. This talk will also report the fabrication and characterization of highly porous, stretchable, and conductive polymer nanocomposites embedded with carbon nanotubes (CNTs) for application in flexible lithium-ion batteries. It will be presented that the porous CNT-embedded PDMS nanocomposites are capable of good electrochemical performance with mechanical flexibility, suggesting these nanocomposites could be outstanding anode candidates for use in flexible lithium-ion batteries. Directed self-assembly (DSA) of block copolymers (BCPs) can generate uniform and periodic patterns within guiding templates, and has been one of the promising nanofabrication methodologies for resolving the resolution limit of optical lithography. BCP self-assembly processing is scalable and of low cost, and is well-suited for integration with existing semiconductor manufacturing techniques. This talk will introduce recent research results (of my research group) on the self-assembly of Si-containing block copolymers for the achievement of sub-10 nm resolution, fast pattern generation, transfer-printing capability onto nonplanar substrates, and device applications for nonvolatile memories. An extraordinarily facile nanofabrication approach that enables sub-10 nm resolutions through the synergic combination of nanotransfer printing (nTP) and DSA of block copolymers is also introduced. This simple printing method can be applied on oxides, metals, polymers, and non-planar substrates without pretreatments. This talk will also report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by the self-assembly of Si-containing BCPs. This approach offers a practical pathway to fabricate high-density resistive memory devices without using high-cost lithography and pattern-transfer processes. Finally, this talk will present a novel approach that can relieve the power consumption issue of phase-change memories by incorporating a thin $SiO_x$ layer formed by BCP self-assembly, which locally blocks the contact between a heater electrode and a phase-change material and reduces the phase-change volume. The writing current decreases by 5 times (corresponding to a power reduction of 1/20) as the occupying area fraction of $SiO_x$ nanostructures varies.

• Korean Journal of Materials Research
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• v.19 no.9
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.