• Electrical & Electronic Materials
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• v.10 no.10
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• pp.1029-1033
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• 1997

A prototype MFSFET using ferroelectric fluoride BaMgF$_4$as a gate insulator has been successfully fabricated with the help of 2 sheets of metal mask. The fluoride film was deposited in an ultrai-high vacuum system at a substrate temperature of below 30$0^{\circ}C$ and an in-situ post-deposition annealing was conducted for 20 seconds at $650^{\circ}C$ in the same chamber. The interface state density of the BaMgF$_4$/Si(100) interface calculated by a MFS capacitor fabricated on the same wafer was about 8$\times$10$^{10}$ /cm$^2$.eV. The I$_{D}$-V$_{G}$ characteristics of the MFSFET show a hysteresis loop due to the ferroelectric nature of the BaMgF$_4$film. It is also demonstrated that the I$_{D}$ can be controlled by the “write” plus which was applied before the measurements even at the same “read”gate voltage.ltage.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.476-487
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• 2007

Flash memory offers attractive features, such as non-volatile, shock resistance, fast access, and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, flash memory can only be erased limited number of times. To overcome limitations, flash memory needs a software layer called flash translation layer (FTL). The basic function of FTL is to translate the logical address from the file system like file allocation table (FAT) to the physical address in flash memory. In this paper, a new FTL algorithm called an efficient and advanced space-management technique (EAST) is proposed. EAST improves the performance by optimizing the number of log blocks, by applying the state transition, and by using reallocation blocks. The results of experiments show that EAST outperforms FAST, which is an enhanced log block scheme, particularly when the usage of flash memory is not full.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.103-108
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• 2014

The flash memory which is exploited on hand-held devices such as smart phones is a non-volatile storage and has the benefit that it can store mass data at a small sized chip. To process queries on the mass data stored in the flash memory, the index scheme should be exploited. However, since the write operation of the flash memory is slower than the read operation and the overwrite is not supported, it is required to reevaluate the performance of the index and find out the drawbacks. In this paper, we evaluate the performance of a space division typed index scheme on the flash memory. To do this, we implement the fixed grid file and measure the average speeds of the query and update processing on a various condition and compare the value of the flash memory with that of the magnetic disk.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.5
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• pp.224-230
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• 2001

The characteristics of $NO/N_2O$ annealed reoxidized nitrided oxide being studied as super thin gate oxide and gate dielectric layers of Non-Volatile Semiconductor Memory (NVSM) were investigated by Dynamic Secondary Ion Mass Spectrometry (D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS), and Auger Electron Spectroscopy (AES). The specimen was annealed by $NO/N_2O$ after initial oxide process and then rcoxidized for nitrogen redistribution in nitrided oxide. Out-diffusion of incorporated nitrogen during the wet oxidation in reoxidation process took place more strongly than that of the dry oxidation. It seems to indicate that hydrogen plays a role in breaking the Si N bonds. As reoxidation proceeds, incorporated nitrogen of $NO/N_2O$ annealed nitrided oxide is obsen-ed to diffuse toward the surface and substrate at the same time. ToF-SIMS results show that SiON species are detected at the initialoxide interface, and Si,NO species near the new $Si_2NO$ interface that formed after reoxidation. These SiON and $Si_2NO$ species most likely to relate to the origin of the state of memory charge traps in reoxidized nitrided oxide, because nitrogen dangling bonds of SiON and silicon dangling bonds of $Si_2NO$ are contained defects associated with memory effect.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1270-1272
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• 2003

Smart card system is being used in many countries to improve access to their transportation systems. Especially for subway system that typically see high volumes of passengers at specific times of the days, it's critical to find a ray to collect fares without unnecessarily delaying passengers. The card consists of antenna, modulation and demodulation block, power supply module and memory. The antenna receives the power and data signal from reader. The FRAM is used as the inner memory. And it is a non-volatile memory and complements the problems, that is high consumption and low data processing speed, of using conventional EEPROM in the passive smart cart. In this paper, we analyze and design the RF passive smart card to apply to the fare collection for the subway gate system.

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.20.1-20.1
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• 2011

The nano-sized quantum structure has been an attractive candidate for investigations of the fundamental physical properties and potential applications of next-generation electronic devices. Metal nano-particles form deep quantum wells between control and tunnel oxides due to a difference in work functions. The charge storage capacity of nanoparticles has led to their use in the development of nano-floating gate memory (NFGM) devices. When compared with conventional floating gate memory devices, NFGM devices offer a number of advantages that have attracted a great deal of attention: a greater inherent scalability, better endurance, a faster write/erase speed, and more processes that are compatible with conventional silicon processes. To improve the performance of NFGM, metal nanocrystals such as Au, Ag, Ni Pt, and W have been proposed due to superior density, a strong coupling with the conduction channel, a wide range of work function selectivity, and a small energy perturbation. In the present study, bismuth metal nanocrystals were self-assembled within high-k $Bi_2Mg_{2/3}Nb_{4/3}O_7$ (BMN) films grown at room temperature in Ar ambient via radio-frequency magnetron sputtering. The work function of the bismuth metal nanocrystals (4.34 eV) was important for nanocrystal-based nonvolatile memory (NVM) applications. If transparent NFGM devices can be integrated with transparent solar cells, non-volatile memory fields will open a new platform for flexible electron devices.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.651-660
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• 2008

Flash memory is widely used in embedded systems because of its benefits such as non-volatile, shock resistant, and low power consumption. However, NAND flash memory suffers from out-place-update, limited erase cycles, and page based read/write operations. To solve these problems, YAFFS and RFFS, the flash memory file systems, are proposed. However YAFFS takes long time to mount the file system, because all the files are scattered all around flash memory. Thus YAFFS needs to fully scan the flash memory. To provide fast mounting, RFFS has been proposed. It stores all the block information, the addresses of block information and meta data to use them at mounting time. However additional operations for the meta data management are decreasing the performance of the system. This paper presents a new NAND flash file system called ERFFS (Efficient and Reliable Flash File System) which provides fast mounting and recovery with minimum mata data management. Based on the experimental results, ERFFS reduces the flash mount/recovery time and the file system overhead.

• Journal of KIISE
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• v.42 no.11
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• pp.1314-1321
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• 2015

Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.